TY - GEN
T1 - A Calibrated Memristor Model Implementation for an SR-Latch Based on CMOS-Memristor Technology
AU - Gavilanez, Martin
AU - Guitarra, Silvana
N1 - Publisher Copyright:
© 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - An SR-Latch based on CMOS-memristor technol-ogy has been implemented in LT-spice, employing memristors calibrated with experimental data. Initially, we analyzed the electrical behavior of HfO_2 -based ReRAMs to acquire key parameters essential for calibrating the memristor model. This calibration process generates the inherent variability reported for these devices. After, we build an OR gate with two calibrated memristors that, according to the analysis, work under the logical principles that govern the OR gate operation. Finally, the SR-Latch was implemented at the circuit level in LTspice. The outputs demonstrate that the latch exhibited a high accuracy, which implies that the memristor's variability does not affect the desired operation.
AB - An SR-Latch based on CMOS-memristor technol-ogy has been implemented in LT-spice, employing memristors calibrated with experimental data. Initially, we analyzed the electrical behavior of HfO_2 -based ReRAMs to acquire key parameters essential for calibrating the memristor model. This calibration process generates the inherent variability reported for these devices. After, we build an OR gate with two calibrated memristors that, according to the analysis, work under the logical principles that govern the OR gate operation. Finally, the SR-Latch was implemented at the circuit level in LTspice. The outputs demonstrate that the latch exhibited a high accuracy, which implies that the memristor's variability does not affect the desired operation.
KW - OR gate
KW - ReRAM
KW - SR-Latch
KW - latch
KW - variability
UR - https://www.scopus.com/pages/publications/85192249898
U2 - 10.1109/LASCAS60203.2024.10506178
DO - 10.1109/LASCAS60203.2024.10506178
M3 - Contribución a la conferencia
AN - SCOPUS:85192249898
T3 - LASCAS 2024 - 15th IEEE Latin American Symposium on Circuits and Systems, Proceedings
BT - LASCAS 2024 - 15th IEEE Latin American Symposium on Circuits and Systems, Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 15th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2024
Y2 - 27 February 2024 through 1 March 2024
ER -