A Low-Power 4-bit Tracking-Type Analog-to-Digital Converter in SKY130 Process

Esteban Astudillo; Eduardo Holguín; Esteban Garzón; Luis Miguel Prócel

doi:10.1109/VLSI-SoC64688.2025.11421767

A Low-Power 4-bit Tracking-Type Analog-to-Digital Converter in SKY130 Process

Esteban Astudillo^*
, Eduardo Holguín
, Esteban Garzón
, Luis Miguel Prócel

^*Corresponding author for this work

Universidad San Francisco de Quito
University of Calabria

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper presents the design and full-custom layout implementation of a 4-bit Tracking-Type Analog-to-Digital Converter (TT-ADC) using the SKY130 130 nm CMOS process. The proposed architecture mainly integrates a rail-to-rail analog comparator and a multiplexed resistor-string Digital-to-Analog Converter (DAC), combined with a synchronous controller and an output register. Unlike traditional tracking ADCs, this work introduces a fully integrated mixed-signal design optimized for both bandwidth and power efficiency, and evaluated under process-temperature-voltage variations accounting for layout parasitics. Simulations show that the proposed TT-ADC presents a bandwidth of 150 MHz while consuming only 505 μ of power. Compared to prior 4-bit implementations, the proposed design achieves over 2 × improvement in bandwidth and an 87% reduction in power consumption. The area footprint is about 54.9 μ × 29.3 μ, making it highly suitable for energyconstrained, high-speed embedded applications.

Original language	English
Title of host publication	2025 IFIP/IEEE 33rd International Conference on Very Large Scale Integration, VLSI-SoC 2025
Publisher	IEEE Computer Society
ISBN (Electronic)	9798331598129
DOIs	https://doi.org/10.1109/VLSI-SoC64688.2025.11421767
State	Published - 2025
Event	33rd IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2025 - Puerto Varas, Chile Duration: 12 Oct 2025 → 15 Oct 2025

Publication series

Name	IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
ISSN (Print)	2324-8432
ISSN (Electronic)	2324-8440

Conference

Conference	33rd IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2025
Country/Territory	Chile
City	Puerto Varas
Period	12/10/25 → 15/10/25

Keywords

ADC
Layout
Open-Source
Rail-toRail Comparator
Resistor-String DAC
SKY130
Synchronous Up/Down Counter
TT-ADC

Access to Document

10.1109/VLSI-SoC64688.2025.11421767

Cite this

Astudillo, E., Holguín, E., Garzón, E., & Prócel, L. M. (2025). A Low-Power 4-bit Tracking-Type Analog-to-Digital Converter in SKY130 Process. In 2025 IFIP/IEEE 33rd International Conference on Very Large Scale Integration, VLSI-SoC 2025 (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC). IEEE Computer Society. https://doi.org/10.1109/VLSI-SoC64688.2025.11421767

@inproceedings{badd397c220b4ba5b9b629cdd86478f7,

title = "A Low-Power 4-bit Tracking-Type Analog-to-Digital Converter in SKY130 Process",

abstract = "This paper presents the design and full-custom layout implementation of a 4-bit Tracking-Type Analog-to-Digital Converter (TT-ADC) using the SKY130 130 nm CMOS process. The proposed architecture mainly integrates a rail-to-rail analog comparator and a multiplexed resistor-string Digital-to-Analog Converter (DAC), combined with a synchronous controller and an output register. Unlike traditional tracking ADCs, this work introduces a fully integrated mixed-signal design optimized for both bandwidth and power efficiency, and evaluated under process-temperature-voltage variations accounting for layout parasitics. Simulations show that the proposed TT-ADC presents a bandwidth of 150 MHz while consuming only 505 μ of power. Compared to prior 4-bit implementations, the proposed design achieves over 2 × improvement in bandwidth and an 87\% reduction in power consumption. The area footprint is about 54.9 μ × 29.3 μ, making it highly suitable for energyconstrained, high-speed embedded applications.",

keywords = "ADC, Layout, Open-Source, Rail-toRail Comparator, Resistor-String DAC, SKY130, Synchronous Up/Down Counter, TT-ADC",

author = "Esteban Astudillo and Eduardo Holgu{\'i}n and Esteban Garz{\'o}n and Pr{\'o}cel, \{Luis Miguel\}",

note = "Publisher Copyright: {\textcopyright} 2025 IEEE.; 33rd IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2025 ; Conference date: 12-10-2025 Through 15-10-2025",

year = "2025",

doi = "10.1109/VLSI-SoC64688.2025.11421767",

language = "Ingl{\'e}s",

series = "IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC",

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}

Astudillo, E, Holguín, E, Garzón, E & Prócel, LM 2025, A Low-Power 4-bit Tracking-Type Analog-to-Digital Converter in SKY130 Process. in 2025 IFIP/IEEE 33rd International Conference on Very Large Scale Integration, VLSI-SoC 2025. IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC, IEEE Computer Society, 33rd IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2025, Puerto Varas, Chile, 12/10/25. https://doi.org/10.1109/VLSI-SoC64688.2025.11421767

A Low-Power 4-bit Tracking-Type Analog-to-Digital Converter in SKY130 Process. / Astudillo, Esteban; Holguín, Eduardo; Garzón, Esteban et al.
2025 IFIP/IEEE 33rd International Conference on Very Large Scale Integration, VLSI-SoC 2025. IEEE Computer Society, 2025. (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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T1 - A Low-Power 4-bit Tracking-Type Analog-to-Digital Converter in SKY130 Process

AU - Astudillo, Esteban

AU - Holguín, Eduardo

AU - Garzón, Esteban

AU - Prócel, Luis Miguel

PY - 2025

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N2 - This paper presents the design and full-custom layout implementation of a 4-bit Tracking-Type Analog-to-Digital Converter (TT-ADC) using the SKY130 130 nm CMOS process. The proposed architecture mainly integrates a rail-to-rail analog comparator and a multiplexed resistor-string Digital-to-Analog Converter (DAC), combined with a synchronous controller and an output register. Unlike traditional tracking ADCs, this work introduces a fully integrated mixed-signal design optimized for both bandwidth and power efficiency, and evaluated under process-temperature-voltage variations accounting for layout parasitics. Simulations show that the proposed TT-ADC presents a bandwidth of 150 MHz while consuming only 505 μ of power. Compared to prior 4-bit implementations, the proposed design achieves over 2 × improvement in bandwidth and an 87% reduction in power consumption. The area footprint is about 54.9 μ × 29.3 μ, making it highly suitable for energyconstrained, high-speed embedded applications.

AB - This paper presents the design and full-custom layout implementation of a 4-bit Tracking-Type Analog-to-Digital Converter (TT-ADC) using the SKY130 130 nm CMOS process. The proposed architecture mainly integrates a rail-to-rail analog comparator and a multiplexed resistor-string Digital-to-Analog Converter (DAC), combined with a synchronous controller and an output register. Unlike traditional tracking ADCs, this work introduces a fully integrated mixed-signal design optimized for both bandwidth and power efficiency, and evaluated under process-temperature-voltage variations accounting for layout parasitics. Simulations show that the proposed TT-ADC presents a bandwidth of 150 MHz while consuming only 505 μ of power. Compared to prior 4-bit implementations, the proposed design achieves over 2 × improvement in bandwidth and an 87% reduction in power consumption. The area footprint is about 54.9 μ × 29.3 μ, making it highly suitable for energyconstrained, high-speed embedded applications.

KW - ADC

KW - Layout

KW - Open-Source

KW - Rail-toRail Comparator

KW - Resistor-String DAC

KW - SKY130

KW - Synchronous Up/Down Counter

KW - TT-ADC

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M3 - Contribución a la conferencia

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T3 - IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC

BT - 2025 IFIP/IEEE 33rd International Conference on Very Large Scale Integration, VLSI-SoC 2025

PB - IEEE Computer Society

T2 - 33rd IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2025

Y2 - 12 October 2025 through 15 October 2025

ER -

A Low-Power 4-bit Tracking-Type Analog-to-Digital Converter in SKY130 Process

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Keywords

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