Assessment of 2T2R Logic-in-Memory in a Cycle-to-Cycle Variation-Aware Simulation Environment

Computing-in-memory (CiM) architectures are based on non-volatile memory technologies, such as resistive RAM (ReRAM) ferroelectric (FeFET) and spin-transfer-torque magnetic RAM (STT-MRAM). In particular, ReRAM has been used due to its compatibility with CMOS technology and nonvolatility. This work proposes a calibration with experimental data that includes cycle-to-cycle (C2C) variability of a memristor dynamic model, compatible with a commercial 65nm CMOS technology. A C2C variability-aware model was implemented to analyze and characterize, for the first time, under critical realistic conditions, a 2T2R architecture that supports logic-inmemory (LiM) operations. The current-voltage curves of the memristor dynamic model were calibrated using experimental data from an HfO₂-based 85 × 85 nm²ReRAM device. The 2T2R architecture, that can serve as a high-density storage system as well as an accelerator for data-intensive applications, was assessed for AND, NAND, NOR, OR, and full adder LiM boolean functions. Simulation results verify that the proposed 2T2R structure operates reliably across FF, TT, and SS corners, taking into account C 2 C variability with V_DD down to 0.8 V. Our model demonstrates that the 2T2R architecture can achieve a frequency of 3.2 GHz at V_DD=1.2 V with a power consumption of 198 fJ per cycle of operation, which can be reduced to 69 fJ at V_DD=0.8 V with a maximum operating frequency of 0.57 GHz.