Assessment of STT-MRAM performance at nanoscaled technology nodes using a device-to-memory simulation framework

Esteban Garzón, Raffaele De Rose, Felice Crupi, Lionel Trojman, Marco Lanuzza

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23 Scopus citations

Abstract

This paper deals with the technology scalability of spin-transfer torque magnetic RAMs (STT-MRAMs)based on nanoscaled perpendicular magnetic tunnel junctions (MTJs)and FinFET technology. Our study was performed at different levels of abstraction, from device- up to architecture-level passing through a circuit-level analysis for the single memory bitcell. Simulation results obtained for a 512 KB cache memory show that scaling from the 28-nm down to the 20-nm technology node leads to reduced write latency (−20%)and lower energy consumption under both write (−36%)and read (−29%)accesses, while also ensuring an almost doubled integration density. This occurs at the expense of slightly reduced sensing margins and higher read latency (+5%), and of a degradation in the data retention capability owing to the reduced MTJ thermal stability.

Original languageEnglish
Article number111009
JournalMicroelectronic Engineering
Volume215
DOIs
StatePublished - 15 Jul 2019

Keywords

  • Device-to-memory analysis
  • FinFET
  • Magnetic tunnel junction (MTJ)
  • STT-MRAM
  • Technology scaling

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