TY - GEN
T1 - Design of a real-time simulator for linear circuits
AU - Granda, Santiago
AU - Lopez, Carlos
AU - Sanchez, Alberto
N1 - Publisher Copyright:
© 2020 IEEE.
PY - 2020/10/13
Y1 - 2020/10/13
N2 - This paper presents the design of a real-time simulator for linear circuits of up to ten nodes using a Xilinx Zynq 7010 SoC. The document presents the required concepts related to linear circuit analysis and its associated numerical methods. Then, a conceptual design and its implementation in Verilog is presented. Pre- and post-synthesis simulation results are compared with theoretical PSpice simulation.
AB - This paper presents the design of a real-time simulator for linear circuits of up to ten nodes using a Xilinx Zynq 7010 SoC. The document presents the required concepts related to linear circuit analysis and its associated numerical methods. Then, a conceptual design and its implementation in Verilog is presented. Pre- and post-synthesis simulation results are compared with theoretical PSpice simulation.
UR - http://www.scopus.com/inward/record.url?scp=85098566668&partnerID=8YFLogxK
U2 - 10.1109/ANDESCON50619.2020.9272134
DO - 10.1109/ANDESCON50619.2020.9272134
M3 - Contribución a la conferencia
AN - SCOPUS:85098566668
T3 - 2020 IEEE ANDESCON, ANDESCON 2020
BT - 2020 IEEE ANDESCON, ANDESCON 2020
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2020 IEEE ANDESCON, ANDESCON 2020
Y2 - 13 October 2020 through 16 October 2020
ER -