Energy-Efficient FinFET-Versus TFET-Based STT-MRAM Bitcells

Ariana Musello; Santiago S. Perez; Marco Villegas; Luis Miguel Procel; Ramiro Taco; Lionel Trojman

doi:10.1109/LASCAS53948.2022.9789086

Energy-Efficient FinFET-Versus TFET-Based STT-MRAM Bitcells

Ariana Musello
, Santiago S. Perez
, Marco Villegas
, Luis Miguel Procel
, Ramiro Taco
, Lionel Trojman

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

This paper explores STT-MRAM bitcells based on double-barrier magnetic tunnel junctions (DMTJs) at the circuit-level, benchmarking TFET - against FinFET-based bitcells focusing on their write operation. Different bitcell configurations are tested to find optimal minimum energy design points using both technologies in a range of ultralow supply voltages. TFETs were found to be the optimal access device for supply voltages under or equal to 0.4V because of their significantly more robust behavior and lower write energy consumption, albeit higher write delays and bigger area for higher voltages.

Original language	English
Title of host publication	2022 IEEE 13th Latin American Symposium on Circuits and Systems, LASCAS 2022
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781665420082
DOIs	https://doi.org/10.1109/LASCAS53948.2022.9789086
State	Published - 2022
Event	13th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2022 - Santiago, Chile Duration: 1 Mar 2022 → 4 Mar 2022

Publication series

Name	2022 IEEE 13th Latin American Symposium on Circuits and Systems, LASCAS 2022

Conference

Conference	13th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2022
Country/Territory	Chile
City	Santiago
Period	1/03/22 → 4/03/22

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

FinFET
STT-MRAM
double-barrier magnetic tunnel junction (DMTJ)
tunnel FET (TFET)
ultralow voltage

Access to Document

10.1109/LASCAS53948.2022.9789086

Cite this

Musello, A., Perez, S. S., Villegas, M., Procel, L. M., Taco, R., & Trojman, L. (2022). Energy-Efficient FinFET-Versus TFET-Based STT-MRAM Bitcells. In 2022 IEEE 13th Latin American Symposium on Circuits and Systems, LASCAS 2022 (2022 IEEE 13th Latin American Symposium on Circuits and Systems, LASCAS 2022). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/LASCAS53948.2022.9789086

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title = "Energy-Efficient FinFET-Versus TFET-Based STT-MRAM Bitcells",

abstract = "This paper explores STT-MRAM bitcells based on double-barrier magnetic tunnel junctions (DMTJs) at the circuit-level, benchmarking TFET - against FinFET-based bitcells focusing on their write operation. Different bitcell configurations are tested to find optimal minimum energy design points using both technologies in a range of ultralow supply voltages. TFETs were found to be the optimal access device for supply voltages under or equal to 0.4V because of their significantly more robust behavior and lower write energy consumption, albeit higher write delays and bigger area for higher voltages.",

keywords = "FinFET, STT-MRAM, double-barrier magnetic tunnel junction (DMTJ), tunnel FET (TFET), ultralow voltage",

author = "Ariana Musello and Perez, \{Santiago S.\} and Marco Villegas and Procel, \{Luis Miguel\} and Ramiro Taco and Lionel Trojman",

note = "Publisher Copyright: {\textcopyright} 2022 IEEE.; 13th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2022 ; Conference date: 01-03-2022 Through 04-03-2022",

year = "2022",

doi = "10.1109/LASCAS53948.2022.9789086",

language = "Ingl{\'e}s",

series = "2022 IEEE 13th Latin American Symposium on Circuits and Systems, LASCAS 2022",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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}

Musello, A, Perez, SS, Villegas, M, Procel, LM, Taco, R & Trojman, L 2022, Energy-Efficient FinFET-Versus TFET-Based STT-MRAM Bitcells. in 2022 IEEE 13th Latin American Symposium on Circuits and Systems, LASCAS 2022. 2022 IEEE 13th Latin American Symposium on Circuits and Systems, LASCAS 2022, Institute of Electrical and Electronics Engineers Inc., 13th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2022, Santiago, Chile, 1/03/22. https://doi.org/10.1109/LASCAS53948.2022.9789086

Energy-Efficient FinFET-Versus TFET-Based STT-MRAM Bitcells. / Musello, Ariana; Perez, Santiago S.; Villegas, Marco et al.
2022 IEEE 13th Latin American Symposium on Circuits and Systems, LASCAS 2022. Institute of Electrical and Electronics Engineers Inc., 2022. (2022 IEEE 13th Latin American Symposium on Circuits and Systems, LASCAS 2022).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Energy-Efficient FinFET-Versus TFET-Based STT-MRAM Bitcells

AU - Musello, Ariana

AU - Perez, Santiago S.

AU - Villegas, Marco

AU - Procel, Luis Miguel

AU - Taco, Ramiro

AU - Trojman, Lionel

PY - 2022

Y1 - 2022

N2 - This paper explores STT-MRAM bitcells based on double-barrier magnetic tunnel junctions (DMTJs) at the circuit-level, benchmarking TFET - against FinFET-based bitcells focusing on their write operation. Different bitcell configurations are tested to find optimal minimum energy design points using both technologies in a range of ultralow supply voltages. TFETs were found to be the optimal access device for supply voltages under or equal to 0.4V because of their significantly more robust behavior and lower write energy consumption, albeit higher write delays and bigger area for higher voltages.

AB - This paper explores STT-MRAM bitcells based on double-barrier magnetic tunnel junctions (DMTJs) at the circuit-level, benchmarking TFET - against FinFET-based bitcells focusing on their write operation. Different bitcell configurations are tested to find optimal minimum energy design points using both technologies in a range of ultralow supply voltages. TFETs were found to be the optimal access device for supply voltages under or equal to 0.4V because of their significantly more robust behavior and lower write energy consumption, albeit higher write delays and bigger area for higher voltages.

KW - FinFET

KW - STT-MRAM

KW - double-barrier magnetic tunnel junction (DMTJ)

KW - tunnel FET (TFET)

KW - ultralow voltage

UR - https://www.scopus.com/pages/publications/85133188055

U2 - 10.1109/LASCAS53948.2022.9789086

DO - 10.1109/LASCAS53948.2022.9789086

M3 - Contribución a la conferencia

AN - SCOPUS:85133188055

T3 - 2022 IEEE 13th Latin American Symposium on Circuits and Systems, LASCAS 2022

BT - 2022 IEEE 13th Latin American Symposium on Circuits and Systems, LASCAS 2022

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 13th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2022

Y2 - 1 March 2022 through 4 March 2022

ER -

Musello A, Perez SS, Villegas M, Procel LM, Taco R, Trojman L. Energy-Efficient FinFET-Versus TFET-Based STT-MRAM Bitcells. In 2022 IEEE 13th Latin American Symposium on Circuits and Systems, LASCAS 2022. Institute of Electrical and Electronics Engineers Inc. 2022. (2022 IEEE 13th Latin American Symposium on Circuits and Systems, LASCAS 2022). doi: 10.1109/LASCAS53948.2022.9789086

Energy-Efficient FinFET-Versus TFET-Based STT-MRAM Bitcells

Abstract

Publication series

Conference

UN SDGs

Keywords

Access to Document

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