TY - GEN
T1 - Exploiting Double-Barrier MTJs for Energy-Efficient Nanoscaled STT-MRAMs
AU - Garzón, Esteban
AU - De Rose, Raffaele
AU - Crupi, Felice
AU - Trojman, Lionel
AU - Finocchio, Giovanni
AU - Carpentieri, Mario
AU - Lanuzza, Marco
N1 - Publisher Copyright:
© 2019 IEEE.
PY - 2019/7
Y1 - 2019/7
N2 - This paper explores performance and technology-scalability of STT-MRAMs exploiting double-barrier MTJs (DMTJs) as comparatively evaluated with respect to conventional solution based on single-barrier MTJs (SMTJs). The comparative study was carried out at different design abstraction levels: (i) a bitcell-Ievel analysis relying on the use of Verilog-A compact models, and (ii) an architecture-level analysis for various memory sizes. Overall, our simulation results point out that, thanks to the reduced switching currents, DMTJ-based STT-MRAMs allow reducing write latency of about 60% than their SMTJ-based counterparts. This is achieved while assuring lower energy consumption under both write (-40%) and read (-27%) accesses, at the cost of reduced sensing margins.
AB - This paper explores performance and technology-scalability of STT-MRAMs exploiting double-barrier MTJs (DMTJs) as comparatively evaluated with respect to conventional solution based on single-barrier MTJs (SMTJs). The comparative study was carried out at different design abstraction levels: (i) a bitcell-Ievel analysis relying on the use of Verilog-A compact models, and (ii) an architecture-level analysis for various memory sizes. Overall, our simulation results point out that, thanks to the reduced switching currents, DMTJ-based STT-MRAMs allow reducing write latency of about 60% than their SMTJ-based counterparts. This is achieved while assuring lower energy consumption under both write (-40%) and read (-27%) accesses, at the cost of reduced sensing margins.
KW - Double-barrier magnetic tunnel junction (DMTJ)
KW - FinFET
KW - STT-MRAM
KW - technology-voltage scaling
UR - http://www.scopus.com/inward/record.url?scp=85071584733&partnerID=8YFLogxK
U2 - 10.1109/SMACD.2019.8795223
DO - 10.1109/SMACD.2019.8795223
M3 - Contribución a la conferencia
AN - SCOPUS:85071584733
T3 - SMACD 2019 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Proceedings
SP - 85
EP - 88
BT - SMACD 2019 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2019
Y2 - 15 July 2019 through 18 July 2019
ER -
