Exploiting Double-Barrier MTJs for Energy-Efficient Nanoscaled STT-MRAMs

Esteban Garzón, Raffaele De Rose, Felice Crupi, Lionel Trojman, Giovanni Finocchio, Mario Carpentieri, Marco Lanuzza

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

7 Scopus citations

Abstract

This paper explores performance and technology-scalability of STT-MRAMs exploiting double-barrier MTJs (DMTJs) as comparatively evaluated with respect to conventional solution based on single-barrier MTJs (SMTJs). The comparative study was carried out at different design abstraction levels: (i) a bitcell-Ievel analysis relying on the use of Verilog-A compact models, and (ii) an architecture-level analysis for various memory sizes. Overall, our simulation results point out that, thanks to the reduced switching currents, DMTJ-based STT-MRAMs allow reducing write latency of about 60% than their SMTJ-based counterparts. This is achieved while assuring lower energy consumption under both write (-40%) and read (-27%) accesses, at the cost of reduced sensing margins.

Original languageEnglish
Title of host publicationSMACD 2019 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages85-88
Number of pages4
ISBN (Electronic)9781728112015
DOIs
StatePublished - Jul 2019
Event16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2019 - Lausanne, Switzerland
Duration: 15 Jul 201918 Jul 2019

Publication series

NameSMACD 2019 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Proceedings

Conference

Conference16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2019
Country/TerritorySwitzerland
CityLausanne
Period15/07/1918/07/19

Keywords

  • Double-barrier magnetic tunnel junction (DMTJ)
  • FinFET
  • STT-MRAM
  • technology-voltage scaling

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