Exploiting Double-Barrier MTJs for Energy-Efficient Nanoscaled STT-MRAMs

Esteban Garzón; Raffaele De Rose; Felice Crupi; Lionel Trojman; Giovanni Finocchio; Mario Carpentieri; Marco Lanuzza

doi:10.1109/SMACD.2019.8795223

Exploiting Double-Barrier MTJs for Energy-Efficient Nanoscaled STT-MRAMs

Esteban Garzón
, Raffaele De Rose
, Felice Crupi
, Lionel Trojman
, Giovanni Finocchio
, Mario Carpentieri
, Marco Lanuzza

Universidad San Francisco de Quito USFQ

University of Calabria
University of Messina
Polytechnic University of Bari

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

9 Scopus citations

Abstract

This paper explores performance and technology-scalability of STT-MRAMs exploiting double-barrier MTJs (DMTJs) as comparatively evaluated with respect to conventional solution based on single-barrier MTJs (SMTJs). The comparative study was carried out at different design abstraction levels: (i) a bitcell-Ievel analysis relying on the use of Verilog-A compact models, and (ii) an architecture-level analysis for various memory sizes. Overall, our simulation results point out that, thanks to the reduced switching currents, DMTJ-based STT-MRAMs allow reducing write latency of about 60% than their SMTJ-based counterparts. This is achieved while assuring lower energy consumption under both write (-40%) and read (-27%) accesses, at the cost of reduced sensing margins.

Original language	English
Title of host publication	SMACD 2019 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	85-88
Number of pages	4
ISBN (Electronic)	9781728112015
DOIs	https://doi.org/10.1109/SMACD.2019.8795223
State	Published - Jul 2019
Event	16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2019 - Lausanne, Switzerland Duration: 15 Jul 2019 → 18 Jul 2019

Publication series

Name	SMACD 2019 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Proceedings

Conference

Conference	16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2019
Country/Territory	Switzerland
City	Lausanne
Period	15/07/19 → 18/07/19

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

Double-barrier magnetic tunnel junction (DMTJ)
FinFET
STT-MRAM
technology-voltage scaling

Access to Document

10.1109/SMACD.2019.8795223

Cite this

Garzón, E., De Rose, R., Crupi, F., Trojman, L., Finocchio, G., Carpentieri, M., & Lanuzza, M. (2019). Exploiting Double-Barrier MTJs for Energy-Efficient Nanoscaled STT-MRAMs. In SMACD 2019 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Proceedings (pp. 85-88). Article 8795223 (SMACD 2019 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SMACD.2019.8795223

Garzón, Esteban ; De Rose, Raffaele ; Crupi, Felice et al. / Exploiting Double-Barrier MTJs for Energy-Efficient Nanoscaled STT-MRAMs. SMACD 2019 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2019. pp. 85-88 (SMACD 2019 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Proceedings).

@inproceedings{0202b13e168d4ac084b4bb65b441ffbb,

title = "Exploiting Double-Barrier MTJs for Energy-Efficient Nanoscaled STT-MRAMs",

abstract = "This paper explores performance and technology-scalability of STT-MRAMs exploiting double-barrier MTJs (DMTJs) as comparatively evaluated with respect to conventional solution based on single-barrier MTJs (SMTJs). The comparative study was carried out at different design abstraction levels: (i) a bitcell-Ievel analysis relying on the use of Verilog-A compact models, and (ii) an architecture-level analysis for various memory sizes. Overall, our simulation results point out that, thanks to the reduced switching currents, DMTJ-based STT-MRAMs allow reducing write latency of about 60\% than their SMTJ-based counterparts. This is achieved while assuring lower energy consumption under both write (-40\%) and read (-27\%) accesses, at the cost of reduced sensing margins.",

keywords = "Double-barrier magnetic tunnel junction (DMTJ), FinFET, STT-MRAM, technology-voltage scaling",

author = "Esteban Garz{\'o}n and \{De Rose\}, Raffaele and Felice Crupi and Lionel Trojman and Giovanni Finocchio and Mario Carpentieri and Marco Lanuzza",

note = "Publisher Copyright: {\textcopyright} 2019 IEEE.; 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2019 ; Conference date: 15-07-2019 Through 18-07-2019",

year = "2019",

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doi = "10.1109/SMACD.2019.8795223",

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series = "SMACD 2019 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Proceedings",

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Garzón, E, De Rose, R, Crupi, F, Trojman, L, Finocchio, G, Carpentieri, M & Lanuzza, M 2019, Exploiting Double-Barrier MTJs for Energy-Efficient Nanoscaled STT-MRAMs. in SMACD 2019 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Proceedings., 8795223, SMACD 2019 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Proceedings, Institute of Electrical and Electronics Engineers Inc., pp. 85-88, 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2019, Lausanne, Switzerland, 15/07/19. https://doi.org/10.1109/SMACD.2019.8795223

Exploiting Double-Barrier MTJs for Energy-Efficient Nanoscaled STT-MRAMs. / Garzón, Esteban; De Rose, Raffaele; Crupi, Felice et al.
SMACD 2019 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2019. p. 85-88 8795223 (SMACD 2019 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Exploiting Double-Barrier MTJs for Energy-Efficient Nanoscaled STT-MRAMs

AU - Garzón, Esteban

AU - De Rose, Raffaele

AU - Crupi, Felice

AU - Trojman, Lionel

AU - Finocchio, Giovanni

AU - Carpentieri, Mario

AU - Lanuzza, Marco

PY - 2019/7

Y1 - 2019/7

N2 - This paper explores performance and technology-scalability of STT-MRAMs exploiting double-barrier MTJs (DMTJs) as comparatively evaluated with respect to conventional solution based on single-barrier MTJs (SMTJs). The comparative study was carried out at different design abstraction levels: (i) a bitcell-Ievel analysis relying on the use of Verilog-A compact models, and (ii) an architecture-level analysis for various memory sizes. Overall, our simulation results point out that, thanks to the reduced switching currents, DMTJ-based STT-MRAMs allow reducing write latency of about 60% than their SMTJ-based counterparts. This is achieved while assuring lower energy consumption under both write (-40%) and read (-27%) accesses, at the cost of reduced sensing margins.

AB - This paper explores performance and technology-scalability of STT-MRAMs exploiting double-barrier MTJs (DMTJs) as comparatively evaluated with respect to conventional solution based on single-barrier MTJs (SMTJs). The comparative study was carried out at different design abstraction levels: (i) a bitcell-Ievel analysis relying on the use of Verilog-A compact models, and (ii) an architecture-level analysis for various memory sizes. Overall, our simulation results point out that, thanks to the reduced switching currents, DMTJ-based STT-MRAMs allow reducing write latency of about 60% than their SMTJ-based counterparts. This is achieved while assuring lower energy consumption under both write (-40%) and read (-27%) accesses, at the cost of reduced sensing margins.

KW - Double-barrier magnetic tunnel junction (DMTJ)

KW - FinFET

KW - STT-MRAM

KW - technology-voltage scaling

UR - https://www.scopus.com/pages/publications/85071584733

U2 - 10.1109/SMACD.2019.8795223

DO - 10.1109/SMACD.2019.8795223

M3 - Contribución a la conferencia

AN - SCOPUS:85071584733

T3 - SMACD 2019 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Proceedings

SP - 85

EP - 88

BT - SMACD 2019 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2019

Y2 - 15 July 2019 through 18 July 2019

ER -

Garzón E, De Rose R, Crupi F, Trojman L, Finocchio G, Carpentieri M et al. Exploiting Double-Barrier MTJs for Energy-Efficient Nanoscaled STT-MRAMs. In SMACD 2019 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Proceedings. Institute of Electrical and Electronics Engineers Inc. 2019. p. 85-88. 8795223. (SMACD 2019 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Proceedings). doi: 10.1109/SMACD.2019.8795223

Exploiting Double-Barrier MTJs for Energy-Efficient Nanoscaled STT-MRAMs

Abstract

Publication series

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UN SDGs

Keywords

Access to Document

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