High-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator

Ricardo Escobar; Luis Miguel Procel; Lionel Trojman; Marco Lanuzza; Ramiro Taco

doi:10.1109/LASCAS51355.2021.9459151

High-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator

Ricardo Escobar
, Luis Miguel Procel
, Lionel Trojman
, Marco Lanuzza
, Ramiro Taco

Universidad San Francisco de Quito
Institut Supérieur d'Électronique de Paris (ISEP)
University of Calabria

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

This paper presents an energy-efficient single-clock-cycle binary Dual-Mode Logic (DML)-based comparator optimized to operate in the dynamic mode. The parallel-prefix architecture is implemented to ensure high speed, whereas low power consumption is guaranteed by reducing the switching activities of internal nodes. Domino Logic (DL) and DML implementations are compared in terms of delay and energy for different supply voltages in the 32 nm technology. We demonstrate an average improvement of 5% in both energy and delay when the DML design is operating in the dynamic mode compared to its conventional domino counterpart. Moreover, the DML design operating in the static mode allows to save up to 43% energy consumption compared to the equivalent domino logic-based implementation.

Original language	English
Title of host publication	2021 IEEE 12th Latin American Symposium on Circuits and Systems, LASCAS 2021
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728176703
DOIs	https://doi.org/10.1109/LASCAS51355.2021.9459151
State	Published - 21 Feb 2021
Event	12th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2021 - Arequipa, Peru Duration: 22 Feb 2021 → 25 Feb 2021

Publication series

Name	2021 IEEE 12th Latin American Symposium on Circuits and Systems, LASCAS 2021

Conference

Conference	12th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2021
Country/Territory	Peru
City	Arequipa
Period	22/02/21 → 25/02/21

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

CMOS
Dual-mode logic
arithmetic circuits
binary comparator

Access to Document

10.1109/LASCAS51355.2021.9459151

Cite this

Escobar, R., Procel, L. M., Trojman, L., Lanuzza, M., & Taco, R. (2021). High-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator. In 2021 IEEE 12th Latin American Symposium on Circuits and Systems, LASCAS 2021 Article 9459151 (2021 IEEE 12th Latin American Symposium on Circuits and Systems, LASCAS 2021). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/LASCAS51355.2021.9459151

Escobar, Ricardo ; Procel, Luis Miguel ; Trojman, Lionel et al. / High-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator. 2021 IEEE 12th Latin American Symposium on Circuits and Systems, LASCAS 2021. Institute of Electrical and Electronics Engineers Inc., 2021. (2021 IEEE 12th Latin American Symposium on Circuits and Systems, LASCAS 2021).

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title = "High-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator",

abstract = "This paper presents an energy-efficient single-clock-cycle binary Dual-Mode Logic (DML)-based comparator optimized to operate in the dynamic mode. The parallel-prefix architecture is implemented to ensure high speed, whereas low power consumption is guaranteed by reducing the switching activities of internal nodes. Domino Logic (DL) and DML implementations are compared in terms of delay and energy for different supply voltages in the 32 nm technology. We demonstrate an average improvement of 5\% in both energy and delay when the DML design is operating in the dynamic mode compared to its conventional domino counterpart. Moreover, the DML design operating in the static mode allows to save up to 43\% energy consumption compared to the equivalent domino logic-based implementation.",

keywords = "CMOS, Dual-mode logic, arithmetic circuits, binary comparator",

author = "Ricardo Escobar and Procel, \{Luis Miguel\} and Lionel Trojman and Marco Lanuzza and Ramiro Taco",

note = "Publisher Copyright: {\textcopyright} 2021 IEEE.; 12th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2021 ; Conference date: 22-02-2021 Through 25-02-2021",

year = "2021",

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doi = "10.1109/LASCAS51355.2021.9459151",

language = "Ingl{\'e}s",

series = "2021 IEEE 12th Latin American Symposium on Circuits and Systems, LASCAS 2021",

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Escobar, R, Procel, LM, Trojman, L, Lanuzza, M & Taco, R 2021, High-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator. in 2021 IEEE 12th Latin American Symposium on Circuits and Systems, LASCAS 2021., 9459151, 2021 IEEE 12th Latin American Symposium on Circuits and Systems, LASCAS 2021, Institute of Electrical and Electronics Engineers Inc., 12th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2021, Arequipa, Peru, 22/02/21. https://doi.org/10.1109/LASCAS51355.2021.9459151

High-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator. / Escobar, Ricardo; Procel, Luis Miguel; Trojman, Lionel et al.
2021 IEEE 12th Latin American Symposium on Circuits and Systems, LASCAS 2021. Institute of Electrical and Electronics Engineers Inc., 2021. 9459151 (2021 IEEE 12th Latin American Symposium on Circuits and Systems, LASCAS 2021).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - High-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator

AU - Escobar, Ricardo

AU - Procel, Luis Miguel

AU - Trojman, Lionel

AU - Lanuzza, Marco

AU - Taco, Ramiro

PY - 2021/2/21

Y1 - 2021/2/21

N2 - This paper presents an energy-efficient single-clock-cycle binary Dual-Mode Logic (DML)-based comparator optimized to operate in the dynamic mode. The parallel-prefix architecture is implemented to ensure high speed, whereas low power consumption is guaranteed by reducing the switching activities of internal nodes. Domino Logic (DL) and DML implementations are compared in terms of delay and energy for different supply voltages in the 32 nm technology. We demonstrate an average improvement of 5% in both energy and delay when the DML design is operating in the dynamic mode compared to its conventional domino counterpart. Moreover, the DML design operating in the static mode allows to save up to 43% energy consumption compared to the equivalent domino logic-based implementation.

AB - This paper presents an energy-efficient single-clock-cycle binary Dual-Mode Logic (DML)-based comparator optimized to operate in the dynamic mode. The parallel-prefix architecture is implemented to ensure high speed, whereas low power consumption is guaranteed by reducing the switching activities of internal nodes. Domino Logic (DL) and DML implementations are compared in terms of delay and energy for different supply voltages in the 32 nm technology. We demonstrate an average improvement of 5% in both energy and delay when the DML design is operating in the dynamic mode compared to its conventional domino counterpart. Moreover, the DML design operating in the static mode allows to save up to 43% energy consumption compared to the equivalent domino logic-based implementation.

KW - CMOS

KW - Dual-mode logic

KW - arithmetic circuits

KW - binary comparator

UR - https://www.scopus.com/pages/publications/85113967263

U2 - 10.1109/LASCAS51355.2021.9459151

DO - 10.1109/LASCAS51355.2021.9459151

M3 - Contribución a la conferencia

AN - SCOPUS:85113967263

T3 - 2021 IEEE 12th Latin American Symposium on Circuits and Systems, LASCAS 2021

BT - 2021 IEEE 12th Latin American Symposium on Circuits and Systems, LASCAS 2021

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 12th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2021

Y2 - 22 February 2021 through 25 February 2021

ER -

Escobar R, Procel LM, Trojman L, Lanuzza M, Taco R. High-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator. In 2021 IEEE 12th Latin American Symposium on Circuits and Systems, LASCAS 2021. Institute of Electrical and Electronics Engineers Inc. 2021. 9459151. (2021 IEEE 12th Latin American Symposium on Circuits and Systems, LASCAS 2021). doi: 10.1109/LASCAS51355.2021.9459151

High-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator

Abstract

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UN SDGs

Keywords

Access to Document

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