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MTJ-Based NV-BCAM Design with Dual Voltage Level Control Circuitry

  • Universidad San Francisco de Quito

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

Non-volatile emerging technologies exploiting magnetic tunnel junction (MTJ) capabilities are presented as promising alternatives to conventional Content Addressable Memories (CAMs). In this paper, an eight-transistor-two-MTJ (8T2MTJ) NV Binary CAM based on a voltage-divider configuration is proposed along with a Dual Voltage Level Control Circuitry (DVLCC) and periphery design to drive search and write control signals through the Searchline. The design was evaluated under nominal, as well as mismatch and process variation through 1000 Monte Carlo simulations for write and search delay, energy, search error rate (SER), and search stability margins. In particular, compared to state-of-the-art designs, the proposed 144-bit NV-BCAM offers lower (1.8%) SER, at the expense of a slight increase in search delay and search energy per bit. However, our design offers DVLCC which allows combined search and write operations through a single VDD supply.

Original languageEnglish
Title of host publication2025 IEEE 16th Latin American Symposium on Circuits and Systems, LASCAS 2025 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9798331522124
DOIs
StatePublished - 2025
Event16th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2025 - Bento Goncalves, Brazil
Duration: 25 Feb 202528 Feb 2025

Publication series

Name2025 IEEE 16th Latin American Symposium on Circuits and Systems, LASCAS 2025 - Proceedings

Conference

Conference16th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2025
Country/TerritoryBrazil
CityBento Goncalves
Period25/02/2528/02/25

Keywords

  • BCAM
  • CAM
  • DMTJ
  • MTJ
  • binary CAM
  • content-addressable memory
  • magnetic tunnel junction

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