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Optimization of Active Voltage Rectifier / Doubler Designed in 90 nm Technology

  • Universidad San Francisco de Quito
  • Isep - LISITE

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

This paper presents the optimization and comparison of three RF-to-DC circuit designs based on voltage rectifiers/doublers for Energy harvester systems. The first design is a 2-stage Differential Drive Cross-Coupled (DDCC) rectifier, the second one is a DDCC rectifier cascaded with a modified DDCC using a body-biasing technique for both NMOS and PMOS transistors and the third design is a DDCC using 2 pair of access transistors. These designs were simulated (TCAD Synopsys) in 90 nm CMOS Technology with three different output resistances ranging from 50, to 500 kΩ. Power (PCE) and voltage (VCE) conversion efficiencies were extracted and compared at a relatively high frequency (950MHz). The results show that after optimization for PCE, for all resistive loads used the DDCC with and without body biasing reach the best PCE% (70%) making these circuits good full wave rectifiers. However, design three gets the best VCE, enabling to properly duplicate the input voltage as required of any voltage doubler circuit.

Original languageEnglish
Title of host publication2020 IEEE 11th Latin American Symposium on Circuits and Systems, LASCAS 2020
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728134277
DOIs
StatePublished - Feb 2020
Event11th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2020 - San Jose, Costa Rica
Duration: 25 Feb 202028 Feb 2020

Publication series

Name2020 IEEE 11th Latin American Symposium on Circuits and Systems, LASCAS 2020

Conference

Conference11th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2020
Country/TerritoryCosta Rica
CitySan Jose
Period25/02/2028/02/20

Keywords

  • Body biasing
  • Energy harvesters
  • Integrated circuit
  • RF-to-dc conversion
  • Rectifier

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