Performance Benchmarking of FinFET- and TFET-Based STT-MRAM Bitcells Operating at Ultra-Low Voltages

Santiago S. Pérez; Alessandro Bedoya; Luis Miguel Prócel; Ramiro Taco

doi:10.1109/lascas56464.2023.10108163

Performance Benchmarking of FinFET- and TFET-Based STT-MRAM Bitcells Operating at Ultra-Low Voltages

Santiago S. Pérez
, Alessandro Bedoya
, Luis Miguel Prócel
, Ramiro Taco

Universidad San Francisco de Quito

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

STT-MRAMs have emerged as the leading candidate of on-chip technology for nonvolatile cache applications. In this paper, DMTJs are used to build STT-MRAMs at the circuit level with a reduced switching current benchmarking the TFET technology model and a calibrated 10nm-FinFET technology model to explore the best configuration in the ultralow voltage domain for writing operation in terms of energy-efficiency and area. Simulation results showed that the TFET-based solutions are the most energy-efficiency in terms of the EDP index with an average EDP 57.77% lower than the FinFET-based configurations. TFET-based bitcells had a 40.23% smaller delay and 34.11% less writing energy compared to the FinFET counterparts. Finally, a standby power analysis was carried out.

Original language	English
Title of host publication	LASCAS 2023 - 14th IEEE Latin American Symposium on Circuits and Systems, Proceedings
Editors	Monica Karel Huerta
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781665457057
DOIs	https://doi.org/10.1109/lascas56464.2023.10108163
State	Published - 2023
Event	14th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2023 - Quito, Ecuador Duration: 27 Feb 2023 → 3 Mar 2023

Publication series

Name	2023 IEEE 14th Latin America Symposium on Circuits and Systems (LASCAS)

Conference

Conference	14th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2023
Country/Territory	Ecuador
City	Quito
Period	27/02/23 → 3/03/23

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

DMTJ
Fin-FET
MTJ
Magnetic Tunnel Junction
STT-MRAM
Spintronics
TFET
Tunnel FET
leakage current

Access to Document

10.1109/lascas56464.2023.10108163

Cite this

Pérez, S. S., Bedoya, A., Prócel, L. M., & Taco, R. (2023). Performance Benchmarking of FinFET- and TFET-Based STT-MRAM Bitcells Operating at Ultra-Low Voltages. In M. K. Huerta (Ed.), LASCAS 2023 - 14th IEEE Latin American Symposium on Circuits and Systems, Proceedings (2023 IEEE 14th Latin America Symposium on Circuits and Systems (LASCAS)). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/lascas56464.2023.10108163

Pérez, Santiago S. ; Bedoya, Alessandro ; Prócel, Luis Miguel et al. / Performance Benchmarking of FinFET- and TFET-Based STT-MRAM Bitcells Operating at Ultra-Low Voltages. LASCAS 2023 - 14th IEEE Latin American Symposium on Circuits and Systems, Proceedings. editor / Monica Karel Huerta. Institute of Electrical and Electronics Engineers Inc., 2023. (2023 IEEE 14th Latin America Symposium on Circuits and Systems (LASCAS)).

@inproceedings{a86fc75022ca468080cb9dea6a1a9e3d,

title = "Performance Benchmarking of FinFET- and TFET-Based STT-MRAM Bitcells Operating at Ultra-Low Voltages",

abstract = "STT-MRAMs have emerged as the leading candidate of on-chip technology for nonvolatile cache applications. In this paper, DMTJs are used to build STT-MRAMs at the circuit level with a reduced switching current benchmarking the TFET technology model and a calibrated 10nm-FinFET technology model to explore the best configuration in the ultralow voltage domain for writing operation in terms of energy-efficiency and area. Simulation results showed that the TFET-based solutions are the most energy-efficiency in terms of the EDP index with an average EDP 57.77\% lower than the FinFET-based configurations. TFET-based bitcells had a 40.23\% smaller delay and 34.11\% less writing energy compared to the FinFET counterparts. Finally, a standby power analysis was carried out.",

keywords = "DMTJ, Fin-FET, MTJ, Magnetic Tunnel Junction, STT-MRAM, Spintronics, TFET, Tunnel FET, leakage current",

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year = "2023",

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series = "2023 IEEE 14th Latin America Symposium on Circuits and Systems (LASCAS)",

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Pérez, SS, Bedoya, A, Prócel, LM & Taco, R 2023, Performance Benchmarking of FinFET- and TFET-Based STT-MRAM Bitcells Operating at Ultra-Low Voltages. in MK Huerta (ed.), LASCAS 2023 - 14th IEEE Latin American Symposium on Circuits and Systems, Proceedings. 2023 IEEE 14th Latin America Symposium on Circuits and Systems (LASCAS), Institute of Electrical and Electronics Engineers Inc., 14th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2023, Quito, Ecuador, 27/02/23. https://doi.org/10.1109/lascas56464.2023.10108163

Performance Benchmarking of FinFET- and TFET-Based STT-MRAM Bitcells Operating at Ultra-Low Voltages. / Pérez, Santiago S.; Bedoya, Alessandro; Prócel, Luis Miguel et al.
LASCAS 2023 - 14th IEEE Latin American Symposium on Circuits and Systems, Proceedings. ed. / Monica Karel Huerta. Institute of Electrical and Electronics Engineers Inc., 2023. (2023 IEEE 14th Latin America Symposium on Circuits and Systems (LASCAS)).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Performance Benchmarking of FinFET- and TFET-Based STT-MRAM Bitcells Operating at Ultra-Low Voltages

AU - Pérez, Santiago S.

AU - Bedoya, Alessandro

AU - Prócel, Luis Miguel

AU - Taco, Ramiro

PY - 2023

Y1 - 2023

N2 - STT-MRAMs have emerged as the leading candidate of on-chip technology for nonvolatile cache applications. In this paper, DMTJs are used to build STT-MRAMs at the circuit level with a reduced switching current benchmarking the TFET technology model and a calibrated 10nm-FinFET technology model to explore the best configuration in the ultralow voltage domain for writing operation in terms of energy-efficiency and area. Simulation results showed that the TFET-based solutions are the most energy-efficiency in terms of the EDP index with an average EDP 57.77% lower than the FinFET-based configurations. TFET-based bitcells had a 40.23% smaller delay and 34.11% less writing energy compared to the FinFET counterparts. Finally, a standby power analysis was carried out.

AB - STT-MRAMs have emerged as the leading candidate of on-chip technology for nonvolatile cache applications. In this paper, DMTJs are used to build STT-MRAMs at the circuit level with a reduced switching current benchmarking the TFET technology model and a calibrated 10nm-FinFET technology model to explore the best configuration in the ultralow voltage domain for writing operation in terms of energy-efficiency and area. Simulation results showed that the TFET-based solutions are the most energy-efficiency in terms of the EDP index with an average EDP 57.77% lower than the FinFET-based configurations. TFET-based bitcells had a 40.23% smaller delay and 34.11% less writing energy compared to the FinFET counterparts. Finally, a standby power analysis was carried out.

KW - DMTJ

KW - Fin-FET

KW - MTJ

KW - Magnetic Tunnel Junction

KW - STT-MRAM

KW - Spintronics

KW - TFET

KW - Tunnel FET

KW - leakage current

UR - https://www.scopus.com/pages/publications/85159660176

U2 - 10.1109/lascas56464.2023.10108163

DO - 10.1109/lascas56464.2023.10108163

M3 - Contribución a la conferencia

AN - SCOPUS:85159660176

T3 - 2023 IEEE 14th Latin America Symposium on Circuits and Systems (LASCAS)

BT - LASCAS 2023 - 14th IEEE Latin American Symposium on Circuits and Systems, Proceedings

A2 - Huerta, Monica Karel

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 14th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2023

Y2 - 27 February 2023 through 3 March 2023

ER -

Pérez SS, Bedoya A, Prócel LM, Taco R. Performance Benchmarking of FinFET- and TFET-Based STT-MRAM Bitcells Operating at Ultra-Low Voltages. In Huerta MK, editor, LASCAS 2023 - 14th IEEE Latin American Symposium on Circuits and Systems, Proceedings. Institute of Electrical and Electronics Engineers Inc. 2023. (2023 IEEE 14th Latin America Symposium on Circuits and Systems (LASCAS)). doi: 10.1109/lascas56464.2023.10108163

Performance Benchmarking of FinFET- and TFET-Based STT-MRAM Bitcells Operating at Ultra-Low Voltages

Abstract

Publication series

Conference

UN SDGs

Keywords

Access to Document

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