Power and Area Reduction of MD5 based on Cryptoprocessor Using novel approach of Internal Counters on the Finite State Machine

Juan Jose Jimenez, Lionel Trojman, Luis Miguel Procel

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

This work presents the design of a very simple microprocessor dedicated to cryptographic operations implementing Message Digest Algorithm 5 (MD5). We tested two control types based on the Moore Finite State Machine: with and without registers as counters. The design was performed with Synopsys TCAD using an open source 500nm technology iPDK. The design using FSM with registers as internal counter results a reduction of 13% on the Silicon area and the simulation demonstrates that we could reach a reduction of 22% of power consumption explained by an 8% decrease of cells required for encryption operations.

Original languageEnglish
Title of host publication2019 IEEE 4th Ecuador Technical Chapters Meeting, ETCM 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728137643
DOIs
StatePublished - Nov 2019
Event4th IEEE Ecuador Technical Chapters Meeting, ETCM 2019 - Guayaquil, Ecuador
Duration: 13 Nov 201915 Nov 2019

Publication series

Name2019 IEEE 4th Ecuador Technical Chapters Meeting, ETCM 2019

Conference

Conference4th IEEE Ecuador Technical Chapters Meeting, ETCM 2019
Country/TerritoryEcuador
CityGuayaquil
Period13/11/1915/11/19

Keywords

  • Area Reduction
  • Integrated Circuit
  • MD5
  • Power Optimization
  • Synopsis
  • System Verilog
  • Top-Down Design

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