XNOR-Bitcount Operation Exploiting Computing-In-Memory With STT-MRAMs

Ariana Musello, Esteban Garzon, Marco Lanuzza, Luis Miguel Procel, Ramiro Taco

Research output: Contribution to journalArticlepeer-review

10 Scopus citations


This brief presents an energy-efficient and high-performance XNOR-bitcount architecture exploiting the benefits of computing-in-memory (CiM) and unique properties of spin-transfer torque magnetic RAM (STT-MRAM) based on double-barrier magnetic tunnel junctions (DMTJs). Our work proposes hardware and algorithmic optimizations, benchmarked against a state-of-the-art CiM-based XNOR-bitcount design. Simulation results show that our hardware optimization reduces the storage requirement (-50%) for each XNOR-bitcount operation. The proposed algorithmic optimization improves execution time and energy consumption by about 30% (78%) and 26% (85%), respectively, for single (5 sequential) 9-bit XNOR-bitcount operations. As a case study, our solution is demonstrated for shape analysis using bit-quads.

Original languageEnglish
Pages (from-to)1259-1263
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Issue number3
StatePublished - 1 Mar 2023


  • BNN
  • CNN
  • Computing-in-memory
  • DMTJ
  • MAC
  • XNOR-bitcount
  • bit-quad
  • spin-transfer torque


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