A 0.8-V, 1.54-pJ/940-MHz Dual-Mode Logic-Based 16×16-b Booth Multiplier in 16-nm FinFET

Netanel Shavit, Inbal Stanger, Ramiro Taco, Marco Lanuzza, Alexander Fish

Producción científica: Contribución a una revistaArtículorevisión exhaustiva

16 Citas (Scopus)

Resumen

The dual-mode logic (DML) defines runtime adapted digital architectures that switch to either improved performance or lower energy consumption as a function of the actual computational workload. This flexibility is demonstrated for the first time by silicon measurements on a 16\times 16 -b Booth multiplier fabricated as a part of an ultralow-power digital signal processing (DSP) architecture for 16-nm FinFET technology. When running in the full-speed mode, the DML multiplier can achieve a performance boost of 19.5% as compared to the equivalent standard CMOS design. The same circuit saves precious energy (-27%, on average) when the energy-efficient mode is enabled, while occupying 13% less silicon area.

Idioma originalInglés
Número de artículo9146537
Páginas (desde-hasta)314-317
Número de páginas4
PublicaciónIEEE Solid-State Circuits Letters
Volumen3
DOI
EstadoPublicada - 2020
Publicado de forma externa

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