Assessment of 10 nm Tunnel-FETs and FinFETs transistors for ultra-low voltage and high-speed digital circuits

Mateo Rendón, Christian Cao, Kevin Landázuri, Luis Miguel Prócel, Lionel Trojman, Ramiro Taco

Producción científica: Capítulo del libro/informe/acta de congresoContribución a la conferenciarevisión exhaustiva

Resumen

The trade-offs of the Tunnel-FETs (TFETs) in terms of delay, energy per cycle, and noise margin are compared with 10 nm FinFETs for a wide voltage supply ranging from 200 to 600 mV with a specific focus on the ultra-low voltage domain. A calibration process is carried out to ensure the same off-current and extrinsic capacitance in both devices. The TFETs presented a high advantage in terms of delay as well as a penalty in energy consumed. As a result, the TFET circuits show a better Energy-Delay trade-off in voltages as low as 350 m V. This is explained by a larger capacitance caused by the nature of the intrinsic materials chosen of the device modelling.

Idioma originalInglés
Título de la publicación alojadaETCM 2021 - 5th Ecuador Technical Chapters Meeting
EditoresMonica Karel Huerta, Sebastian Quevedo, Carlos Monsalve
EditorialInstitute of Electrical and Electronics Engineers Inc.
ISBN (versión digital)9781665441414
DOI
EstadoPublicada - 12 oct. 2021
Evento5th IEEE Ecuador Technical Chapters Meeting, ETCM 2021 - Cuenca, Ecuador
Duración: 12 oct. 202115 oct. 2021

Serie de la publicación

NombreETCM 2021 - 5th Ecuador Technical Chapters Meeting

Conferencia

Conferencia5th IEEE Ecuador Technical Chapters Meeting, ETCM 2021
País/TerritorioEcuador
CiudadCuenca
Período12/10/2115/10/21

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