Assessment of STT-MRAMs based on double-barrier MTJs for cache applications by means of a device-to-system level simulation framework

Esteban Garzón, Raffaele De Rose, Felice Crupi, Lionel Trojman, Giovanni Finocchio, Mario Carpentieri, Marco Lanuzza

Producción científica: Contribución a una revistaArtículorevisión exhaustiva

21 Citas (Scopus)

Resumen

This paper explores non-volatile cache memories implemented by spin-transfer torque magnetic random access memories (STT-MRAMs) based on state-of-the-art perpendicular magnetic tunnel junctions (MTJs) and FinFETs. The use of double-barrier MTJs with two reference layers (DMTJs) is benchmarked against solutions relying on single-barrier MTJs (SMTJs) at different technology nodes (from 28-nm down to 20-nm). Our study is carried out through a cross-layer simulation platform, starting from the device- up to the system-level. Our results point out that, thanks to the reduced switching currents, DMTJ-based STT-MRAMs allow decreasing write access time of about 63% as compared to their SMTJ-based counterparts. This is achieved while assuring reduced energy consumption under both write (−42%) and read (−28%) accesses, lower area occupancy (−40%) and smaller leakage power (−25%), at the only cost of worsened read access time. This makes DMTJ-based STT-MRAM a promising candidate to replace conventional semiconductor-based cache memory for the next-generation of low-power microprocessors with on-chip non-volatility.

Idioma originalInglés
Páginas (desde-hasta)56-69
Número de páginas14
PublicaciónIntegration
Volumen71
DOI
EstadoPublicada - mar. 2020
Publicado de forma externa

Huella

Profundice en los temas de investigación de 'Assessment of STT-MRAMs based on double-barrier MTJs for cache applications by means of a device-to-system level simulation framework'. En conjunto forman una huella única.

Citar esto