Cross-wafer controlled interface layer thickness variation, and its application to SiO2 / high-κ stack characterisation

B. J. O'Sullivan, V. S. Kaushik, L. A. Ragnarsson, L. Trojman, B. Onsia, N. Van Hoornick, E. Rohr, S. DeGendt, M. Heyns

Producción científica: Capítulo del libro/informe/acta de congresoContribución a la conferenciarevisión exhaustiva

Resumen

A technique has been developed to fabricate transistors using a continuously scaled 0-2.5 nm SiO2 interface layer between a silicon substrate and high-κ dielectric on a single wafer. Transistor results are promising with good mobility values and drive current. The slant etching process has no detrimental effect on the electrical characteristics of the Si/SiO 2 interface. This technique provides a powerful tool to examine the effect of process variations on device performance. It has been used to demonstrate that reducing source/drain anneal temperature, from 1000°C to 700°C, results in a significant mobility degradation, for SiO2 interlayer thickness less than 1.0 nm. Above this thickness, the mobility and DIT are relatively independent of anneal temperature.

Idioma originalInglés
Título de la publicación alojadaESSDERC 2006 - Proceedings of the 36th European Solid-State Device Research Conference
EditorialIEEE Computer Society
Páginas395-398
Número de páginas4
ISBN (versión impresa)1424403014, 9781424403011
DOI
EstadoPublicada - 2006
Publicado de forma externa
EventoESSDERC 2006 - 36th European Solid-State Device Research Conference - Montreux, Suiza
Duración: 19 sep. 200621 sep. 2006

Serie de la publicación

NombreESSDERC 2006 - Proceedings of the 36th European Solid-State Device Research Conference

Conferencia

ConferenciaESSDERC 2006 - 36th European Solid-State Device Research Conference
País/TerritorioSuiza
CiudadMontreux
Período19/09/0621/09/06

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