Dual mode logic address decoder

Leonid Yavits, Ramiro Taco, Netanel Shavit, Inbal Stanger, Alexander Fish

Producción científica: Capítulo del libro/informe/acta de congresoContribución a la conferenciarevisión exhaustiva

6 Citas (Scopus)


Address decoders are integral components of random access memories. In higher-performance computing, the timing of address decoders is often critical, especially in applications such as translation lookaside buffer (TLB) and first level data cache. On the other hand, memory power budget and energy consumption are equally critically important for battery-powered devices. Dual Mode Logic (DML) has been shown to combine the support for both requirements in a single circuit. We present a novel DML based address decoder design and compare it with conventional static CMOS and np-CMOS address decoders. Simulations show that DML based address decoder in dynamic mode achieves 31% lower delay compared to conventional static CMOS implementation. In static mode, DML based address decoder reduces the energy consumption by 29% and reaches 10% lower energy-delay product compared to static CMOS address decoder. This is the first time DML is evaluated in 16nm FinFet process.

Idioma originalInglés
Título de la publicación alojada2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings
EditorialInstitute of Electrical and Electronics Engineers Inc.
ISBN (versión digital)9781728133201
EstadoPublicada - 2020
Evento52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Virtual, Online
Duración: 10 oct. 202021 oct. 2020

Serie de la publicación

NombreProceedings - IEEE International Symposium on Circuits and Systems
ISSN (versión impresa)0271-4310


Conferencia52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020
CiudadVirtual, Online


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