Dual mode logic address decoder

Leonid Yavits; Ramiro Taco; Netanel Shavit; Inbal Stanger; Alexander Fish

Dual mode logic address decoder

Leonid Yavits^*
, Ramiro Taco^*
, Netanel Shavit^*
, Inbal Stanger^*
, Alexander Fish^*

^*Autor correspondiente de este trabajo

Ingeniería Electrónica y Automatización

Bar Ilan University

Producción científica: Capítulo del libro/informe/acta de congreso › Contribución a la conferencia › revisión exhaustiva

10 Citas (Scopus)

Resumen

Address decoders are integral components of random access memories. In higher-performance computing, the timing of address decoders is often critical, especially in applications such as translation lookaside buffer (TLB) and first level data cache. On the other hand, memory power budget and energy consumption are equally critically important for battery-powered devices. Dual Mode Logic (DML) has been shown to combine the support for both requirements in a single circuit. We present a novel DML based address decoder design and compare it with conventional static CMOS and np-CMOS address decoders. Simulations show that DML based address decoder in dynamic mode achieves 31% lower delay compared to conventional static CMOS implementation. In static mode, DML based address decoder reduces the energy consumption by 29% and reaches 10% lower energy-delay product compared to static CMOS address decoder. This is the first time DML is evaluated in 16nm FinFet process.

Idioma original	Inglés
Título de la publicación alojada	2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings
Editorial	Institute of Electrical and Electronics Engineers Inc.
ISBN (versión digital)	9781728133201
Estado	Publicada - 2020
Evento	52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Virtual, Online Duración: 10 oct. 2020 → 21 oct. 2020

Serie de la publicación

Nombre	Proceedings - IEEE International Symposium on Circuits and Systems
Volumen	2020-October
ISSN (versión impresa)	0271-4310

Conferencia

Conferencia	52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020
Ciudad	Virtual, Online
Período	10/10/20 → 21/10/20

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@inproceedings{95f5230d393442dea6400e2db6230c19,

title = "Dual mode logic address decoder",

abstract = "Address decoders are integral components of random access memories. In higher-performance computing, the timing of address decoders is often critical, especially in applications such as translation lookaside buffer (TLB) and first level data cache. On the other hand, memory power budget and energy consumption are equally critically important for battery-powered devices. Dual Mode Logic (DML) has been shown to combine the support for both requirements in a single circuit. We present a novel DML based address decoder design and compare it with conventional static CMOS and np-CMOS address decoders. Simulations show that DML based address decoder in dynamic mode achieves 31\% lower delay compared to conventional static CMOS implementation. In static mode, DML based address decoder reduces the energy consumption by 29\% and reaches 10\% lower energy-delay product compared to static CMOS address decoder. This is the first time DML is evaluated in 16nm FinFet process.",

keywords = "Dual mode logic (DML), Memory address decoder",

author = "Leonid Yavits and Ramiro Taco and Netanel Shavit and Inbal Stanger and Alexander Fish",

note = "Publisher Copyright: {\textcopyright} 2020 IEEE; 52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020 ; Conference date: 10-10-2020 Through 21-10-2020",

year = "2020",

language = "Ingl{\'e}s",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings",

}

Yavits, L, Taco, R, Shavit, N, Stanger, I & Fish, A 2020, Dual mode logic address decoder. En 2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings., 9180587, Proceedings - IEEE International Symposium on Circuits and Systems, vol. 2020-October, Institute of Electrical and Electronics Engineers Inc., 52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020, Virtual, Online, 10/10/20.

Dual mode logic address decoder. / Yavits, Leonid; Taco, Ramiro; Shavit, Netanel et al.
2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2020. 9180587 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2020-October).

Producción científica: Capítulo del libro/informe/acta de congreso › Contribución a la conferencia › revisión exhaustiva

TY - GEN

T1 - Dual mode logic address decoder

AU - Yavits, Leonid

AU - Taco, Ramiro

AU - Shavit, Netanel

AU - Stanger, Inbal

AU - Fish, Alexander

PY - 2020

Y1 - 2020

N2 - Address decoders are integral components of random access memories. In higher-performance computing, the timing of address decoders is often critical, especially in applications such as translation lookaside buffer (TLB) and first level data cache. On the other hand, memory power budget and energy consumption are equally critically important for battery-powered devices. Dual Mode Logic (DML) has been shown to combine the support for both requirements in a single circuit. We present a novel DML based address decoder design and compare it with conventional static CMOS and np-CMOS address decoders. Simulations show that DML based address decoder in dynamic mode achieves 31% lower delay compared to conventional static CMOS implementation. In static mode, DML based address decoder reduces the energy consumption by 29% and reaches 10% lower energy-delay product compared to static CMOS address decoder. This is the first time DML is evaluated in 16nm FinFet process.

AB - Address decoders are integral components of random access memories. In higher-performance computing, the timing of address decoders is often critical, especially in applications such as translation lookaside buffer (TLB) and first level data cache. On the other hand, memory power budget and energy consumption are equally critically important for battery-powered devices. Dual Mode Logic (DML) has been shown to combine the support for both requirements in a single circuit. We present a novel DML based address decoder design and compare it with conventional static CMOS and np-CMOS address decoders. Simulations show that DML based address decoder in dynamic mode achieves 31% lower delay compared to conventional static CMOS implementation. In static mode, DML based address decoder reduces the energy consumption by 29% and reaches 10% lower energy-delay product compared to static CMOS address decoder. This is the first time DML is evaluated in 16nm FinFet process.

KW - Dual mode logic (DML)

KW - Memory address decoder

UR - https://www.scopus.com/pages/publications/85106668183

M3 - Contribución a la conferencia

AN - SCOPUS:85106668183

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

BT - 2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020

Y2 - 10 October 2020 through 21 October 2020

ER -

Dual mode logic address decoder

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