Dynamic gate-level body biasing for subthreshold digital design

Marco Lanuzza, Ramiro Taco, Domenico Albano

Producción científica: Capítulo del libro/informe/acta de congresoContribución a la conferenciarevisión exhaustiva

11 Citas (Scopus)

Resumen

Dynamic gate-level body biasing has been recently proposed as an alternative design methodology for subthreshold logic gates. According to this approach, a simple body biasing circuit, embedded in the logic gate, is exploited to change dynamically the threshold voltage of transistors on the basis of the gate status. This allows fast gate switching, while maintaining high energy efficiency. In this work, the proposed technique is exploited to design a low voltage mirror full-adder. When implemented in a 45 nm commercial technology, the designed circuit is 2 and 1.3 times faster than its standard CMOS and DTMOS counterparts. This is achieved while maintaining the lowest total energy per operation consumption and robustness against temperature and process variations.

Idioma originalInglés
Título de la publicación alojada2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Conference Proceedings
EditorialIEEE Computer Society
ISBN (versión impresa)9781479925070
DOI
EstadoPublicada - 2014
Publicado de forma externa
Evento2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Santiago, Chile
Duración: 25 feb. 201428 feb. 2014

Serie de la publicación

Nombre2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Conference Proceedings

Conferencia

Conferencia2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014
País/TerritorioChile
CiudadSantiago
Período25/02/1428/02/14

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