Energy-delay tradeoffs of low-voltage dual mode logic in 28nm FD-SOI

Ramiro Taco, Itamar Levi, Marco Lanuzza, Alexander Fish

Producción científica: Capítulo del libro/informe/acta de congresoContribución a la conferenciarevisión exhaustiva

1 Cita (Scopus)

Resumen

In this paper, the Dual Mode Logic (DML) technique is evaluated on a low-voltage 16-bit Carry Skip Adder in 28 nm UTBB FD-SOI technology. By combining the operating characteristics of the DML and the unique features of the technology, energy/speed efficient low-voltage adder designs can be defined. More precisely, it is demonstrated that, the capability of the DML design to switch on-the-fly between static and dynamic modes of operation leads to an improvement of more than 20% in terms of energy-delay product (EDP) in comparison to the conventional CMOS design. Moreover, the high efficiency of back plane biasing in the adopted technology allows very fine tuning of energy-delay performances of a DML design, thus emphasizing its intrinsic versatility.

Idioma originalInglés
Título de la publicación alojada2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017
EditorialInstitute of Electrical and Electronics Engineers Inc.
Páginas1-3
Número de páginas3
ISBN (versión digital)9781538637654
DOI
EstadoPublicada - 2 jul. 2017
Publicado de forma externa
Evento2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017 - Burlingame, Estados Unidos
Duración: 16 oct. 201718 oct. 2017

Serie de la publicación

Nombre2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017
Volumen2018-March

Conferencia

Conferencia2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017
País/TerritorioEstados Unidos
CiudadBurlingame
Período16/10/1718/10/17

Huella

Profundice en los temas de investigación de 'Energy-delay tradeoffs of low-voltage dual mode logic in 28nm FD-SOI'. En conjunto forman una huella única.

Citar esto