Energy-Efficient FinFET-Versus TFET-Based STT-MRAM Bitcells

Ariana Musello, Santiago S. Perez, Marco Villegas, Luis Miguel Procel, Ramiro Taco, Lionel Trojman

Producción científica: Capítulo del libro/informe/acta de congresoContribución a la conferenciarevisión exhaustiva

2 Citas (Scopus)

Resumen

This paper explores STT-MRAM bitcells based on double-barrier magnetic tunnel junctions (DMTJs) at the circuit-level, benchmarking TFET - against FinFET-based bitcells focusing on their write operation. Different bitcell configurations are tested to find optimal minimum energy design points using both technologies in a range of ultralow supply voltages. TFETs were found to be the optimal access device for supply voltages under or equal to 0.4V because of their significantly more robust behavior and lower write energy consumption, albeit higher write delays and bigger area for higher voltages.

Idioma originalInglés
Título de la publicación alojada2022 IEEE 13th Latin American Symposium on Circuits and Systems, LASCAS 2022
EditorialInstitute of Electrical and Electronics Engineers Inc.
ISBN (versión digital)9781665420082
DOI
EstadoPublicada - 2022
Evento13th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2022 - Santiago, Chile
Duración: 1 mar. 20224 mar. 2022

Serie de la publicación

Nombre2022 IEEE 13th Latin American Symposium on Circuits and Systems, LASCAS 2022

Conferencia

Conferencia13th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2022
País/TerritorioChile
CiudadSantiago
Período1/03/224/03/22

Huella

Profundice en los temas de investigación de 'Energy-Efficient FinFET-Versus TFET-Based STT-MRAM Bitcells'. En conjunto forman una huella única.

Citar esto