Evaluation of Dual Mode Logic in 28nm FD-SOI technology

Ramiro Taco, Itamar Levi, Marco Lanuzza, Alexander Fish

Producción científica: Capítulo del libro/informe/acta de congresoContribución a la conferenciarevisión exhaustiva

14 Citas (Scopus)

Resumen

For the first time, the Dual Mode Logic (DML) technique is evaluated in 28 nm UTBB FD-SOI technology, with the goal of improving energy efficiency for wide supply voltage operation range. By combining the operating characteristics of the DML and the extended body bias capability of the technology, energy efficient digital circuits that can effectively benefit from adaptive voltage and frequency scaling techniques can be defined. This manuscript reports evaluations of the DML against conventional static and dynamic CMOS logics for two benchmarks in the 0.3V-1V supply voltage range. First, a NAND-NOR chain was considered. Simulation results showed that the DML approach assures roughly the 40% savings in terms of energy consumption with respect to the static CMOS implementation and improves the speed about 20% in comparison to the dynamic CMOS design. Second, a 16-bit Carry Skip Adder was considered. Due to the unique capability of the DML to switch on-the-fly between static and dynamic modes of operation, an improvement of more than 20% in terms of EDP was obtained in comparison to the conventional CMOS adder design.

Idioma originalInglés
Título de la publicación alojadaIEEE International Symposium on Circuits and Systems
Subtítulo de la publicación alojadaFrom Dreams to Innovation, ISCAS 2017 - Conference Proceedings
EditorialInstitute of Electrical and Electronics Engineers Inc.
ISBN (versión digital)9781467368520
DOI
EstadoPublicada - 25 sep. 2017
Publicado de forma externa
Evento50th IEEE International Symposium on Circuits and Systems, ISCAS 2017 - Baltimore, Estados Unidos
Duración: 28 may. 201731 may. 2017

Serie de la publicación

NombreProceedings - IEEE International Symposium on Circuits and Systems
ISSN (versión impresa)0271-4310

Conferencia

Conferencia50th IEEE International Symposium on Circuits and Systems, ISCAS 2017
País/TerritorioEstados Unidos
CiudadBaltimore
Período28/05/1731/05/17

Huella

Profundice en los temas de investigación de 'Evaluation of Dual Mode Logic in 28nm FD-SOI technology'. En conjunto forman una huella única.

Citar esto