Exploiting Double-Barrier MTJs for Energy-Efficient Nanoscaled STT-MRAMs

Esteban Garzón; Raffaele De Rose; Felice Crupi; Lionel Trojman; Giovanni Finocchio; Mario Carpentieri; Marco Lanuzza

doi:10.1109/SMACD.2019.8795223

Exploiting Double-Barrier MTJs for Energy-Efficient Nanoscaled STT-MRAMs

Esteban Garzón
, Raffaele De Rose
, Felice Crupi
, Lionel Trojman
, Giovanni Finocchio
, Mario Carpentieri
, Marco Lanuzza

Universidad San Francisco de Quito USFQ

University of Calabria
University of Messina
Polytechnic University of Bari

Producción científica: Capítulo del libro/informe/acta de congreso › Contribución a la conferencia › revisión exhaustiva

9 Citas (Scopus)

Resumen

This paper explores performance and technology-scalability of STT-MRAMs exploiting double-barrier MTJs (DMTJs) as comparatively evaluated with respect to conventional solution based on single-barrier MTJs (SMTJs). The comparative study was carried out at different design abstraction levels: (i) a bitcell-Ievel analysis relying on the use of Verilog-A compact models, and (ii) an architecture-level analysis for various memory sizes. Overall, our simulation results point out that, thanks to the reduced switching currents, DMTJ-based STT-MRAMs allow reducing write latency of about 60% than their SMTJ-based counterparts. This is achieved while assuring lower energy consumption under both write (-40%) and read (-27%) accesses, at the cost of reduced sensing margins.

Idioma original	Inglés
Título de la publicación alojada	SMACD 2019 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Proceedings
Editorial	Institute of Electrical and Electronics Engineers Inc.
Páginas	85-88
Número de páginas	4
ISBN (versión digital)	9781728112015
DOI	https://doi.org/10.1109/SMACD.2019.8795223
Estado	Publicada - jul. 2019
Evento	16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2019 - Lausanne, Suiza Duración: 15 jul. 2019 → 18 jul. 2019

Serie de la publicación

Nombre	SMACD 2019 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Proceedings

Conferencia

Conferencia	16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2019
País/Territorio	Suiza
Ciudad	Lausanne
Período	15/07/19 → 18/07/19

ODS de las Naciones Unidas

Este resultado contribuye a los siguientes Objetivos de Desarrollo Sostenible

ODS 7: Energía asequible y no contaminante

Acceder al documento

10.1109/SMACD.2019.8795223

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Garzón, E., De Rose, R., Crupi, F., Trojman, L., Finocchio, G., Carpentieri, M., & Lanuzza, M. (2019). Exploiting Double-Barrier MTJs for Energy-Efficient Nanoscaled STT-MRAMs. En SMACD 2019 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Proceedings (pp. 85-88). Artículo 8795223 (SMACD 2019 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SMACD.2019.8795223

Garzón, Esteban ; De Rose, Raffaele ; Crupi, Felice et al. / Exploiting Double-Barrier MTJs for Energy-Efficient Nanoscaled STT-MRAMs. SMACD 2019 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2019. pp. 85-88 (SMACD 2019 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Proceedings).

@inproceedings{0202b13e168d4ac084b4bb65b441ffbb,

title = "Exploiting Double-Barrier MTJs for Energy-Efficient Nanoscaled STT-MRAMs",

abstract = "This paper explores performance and technology-scalability of STT-MRAMs exploiting double-barrier MTJs (DMTJs) as comparatively evaluated with respect to conventional solution based on single-barrier MTJs (SMTJs). The comparative study was carried out at different design abstraction levels: (i) a bitcell-Ievel analysis relying on the use of Verilog-A compact models, and (ii) an architecture-level analysis for various memory sizes. Overall, our simulation results point out that, thanks to the reduced switching currents, DMTJ-based STT-MRAMs allow reducing write latency of about 60\% than their SMTJ-based counterparts. This is achieved while assuring lower energy consumption under both write (-40\%) and read (-27\%) accesses, at the cost of reduced sensing margins.",

keywords = "Double-barrier magnetic tunnel junction (DMTJ), FinFET, STT-MRAM, technology-voltage scaling",

author = "Esteban Garz{\'o}n and \{De Rose\}, Raffaele and Felice Crupi and Lionel Trojman and Giovanni Finocchio and Mario Carpentieri and Marco Lanuzza",

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Garzón, E, De Rose, R, Crupi, F, Trojman, L, Finocchio, G, Carpentieri, M & Lanuzza, M 2019, Exploiting Double-Barrier MTJs for Energy-Efficient Nanoscaled STT-MRAMs. En SMACD 2019 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Proceedings., 8795223, SMACD 2019 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Proceedings, Institute of Electrical and Electronics Engineers Inc., pp. 85-88, 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2019, Lausanne, Suiza, 15/07/19. https://doi.org/10.1109/SMACD.2019.8795223

Exploiting Double-Barrier MTJs for Energy-Efficient Nanoscaled STT-MRAMs. / Garzón, Esteban; De Rose, Raffaele; Crupi, Felice et al.
SMACD 2019 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2019. p. 85-88 8795223 (SMACD 2019 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Proceedings).

Producción científica: Capítulo del libro/informe/acta de congreso › Contribución a la conferencia › revisión exhaustiva

TY - GEN

T1 - Exploiting Double-Barrier MTJs for Energy-Efficient Nanoscaled STT-MRAMs

AU - Garzón, Esteban

AU - De Rose, Raffaele

AU - Crupi, Felice

AU - Trojman, Lionel

AU - Finocchio, Giovanni

AU - Carpentieri, Mario

AU - Lanuzza, Marco

PY - 2019/7

Y1 - 2019/7

N2 - This paper explores performance and technology-scalability of STT-MRAMs exploiting double-barrier MTJs (DMTJs) as comparatively evaluated with respect to conventional solution based on single-barrier MTJs (SMTJs). The comparative study was carried out at different design abstraction levels: (i) a bitcell-Ievel analysis relying on the use of Verilog-A compact models, and (ii) an architecture-level analysis for various memory sizes. Overall, our simulation results point out that, thanks to the reduced switching currents, DMTJ-based STT-MRAMs allow reducing write latency of about 60% than their SMTJ-based counterparts. This is achieved while assuring lower energy consumption under both write (-40%) and read (-27%) accesses, at the cost of reduced sensing margins.

AB - This paper explores performance and technology-scalability of STT-MRAMs exploiting double-barrier MTJs (DMTJs) as comparatively evaluated with respect to conventional solution based on single-barrier MTJs (SMTJs). The comparative study was carried out at different design abstraction levels: (i) a bitcell-Ievel analysis relying on the use of Verilog-A compact models, and (ii) an architecture-level analysis for various memory sizes. Overall, our simulation results point out that, thanks to the reduced switching currents, DMTJ-based STT-MRAMs allow reducing write latency of about 60% than their SMTJ-based counterparts. This is achieved while assuring lower energy consumption under both write (-40%) and read (-27%) accesses, at the cost of reduced sensing margins.

KW - Double-barrier magnetic tunnel junction (DMTJ)

KW - FinFET

KW - STT-MRAM

KW - technology-voltage scaling

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U2 - 10.1109/SMACD.2019.8795223

DO - 10.1109/SMACD.2019.8795223

M3 - Contribución a la conferencia

AN - SCOPUS:85071584733

T3 - SMACD 2019 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Proceedings

SP - 85

EP - 88

BT - SMACD 2019 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2019

Y2 - 15 July 2019 through 18 July 2019

ER -

Garzón E, De Rose R, Crupi F, Trojman L, Finocchio G, Carpentieri M et al. Exploiting Double-Barrier MTJs for Energy-Efficient Nanoscaled STT-MRAMs. En SMACD 2019 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Proceedings. Institute of Electrical and Electronics Engineers Inc. 2019. p. 85-88. 8795223. (SMACD 2019 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Proceedings). doi: 10.1109/SMACD.2019.8795223

Exploiting Double-Barrier MTJs for Energy-Efficient Nanoscaled STT-MRAMs

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