High-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator

This paper presents an energy-efficient single-clock-cycle binary Dual-Mode Logic (DML)-based comparator optimized to operate in the dynamic mode. The parallel-prefix architecture is implemented to ensure high speed, whereas low power consumption is guaranteed by reducing the switching activities of internal nodes. Domino Logic (DL) and DML implementations are compared in terms of delay and energy for different supply voltages in the 32 nm technology. We demonstrate an average improvement of 5% in both energy and delay when the DML design is operating in the dynamic mode compared to its conventional domino counterpart. Moreover, the DML design operating in the static mode allows to save up to 43% energy consumption compared to the equivalent domino logic-based implementation.