High-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator

Ricardo Escobar; Luis Miguel Procel; Lionel Trojman; Marco Lanuzza; Ramiro Taco

doi:10.1109/LASCAS51355.2021.9459151

High-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator

Ricardo Escobar
, Luis Miguel Procel
, Lionel Trojman
, Marco Lanuzza
, Ramiro Taco

Universidad San Francisco de Quito
Institut Supérieur d'Électronique de Paris (ISEP)
University of Calabria

Producción científica: Capítulo del libro/informe/acta de congreso › Contribución a la conferencia › revisión exhaustiva

3 Citas (Scopus)

Resumen

This paper presents an energy-efficient single-clock-cycle binary Dual-Mode Logic (DML)-based comparator optimized to operate in the dynamic mode. The parallel-prefix architecture is implemented to ensure high speed, whereas low power consumption is guaranteed by reducing the switching activities of internal nodes. Domino Logic (DL) and DML implementations are compared in terms of delay and energy for different supply voltages in the 32 nm technology. We demonstrate an average improvement of 5% in both energy and delay when the DML design is operating in the dynamic mode compared to its conventional domino counterpart. Moreover, the DML design operating in the static mode allows to save up to 43% energy consumption compared to the equivalent domino logic-based implementation.

Idioma original	Inglés
Título de la publicación alojada	2021 IEEE 12th Latin American Symposium on Circuits and Systems, LASCAS 2021
Editorial	Institute of Electrical and Electronics Engineers Inc.
ISBN (versión digital)	9781728176703
DOI	https://doi.org/10.1109/LASCAS51355.2021.9459151
Estado	Publicada - 21 feb. 2021
Evento	12th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2021 - Arequipa, Perú Duración: 22 feb. 2021 → 25 feb. 2021

Serie de la publicación

Nombre	2021 IEEE 12th Latin American Symposium on Circuits and Systems, LASCAS 2021

Conferencia

Conferencia	12th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2021
País/Territorio	Perú
Ciudad	Arequipa
Período	22/02/21 → 25/02/21

ODS de las Naciones Unidas

Este resultado contribuye a los siguientes Objetivos de Desarrollo Sostenible

ODS 7: Energía asequible y no contaminante

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10.1109/LASCAS51355.2021.9459151

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Escobar, R., Procel, L. M., Trojman, L., Lanuzza, M., & Taco, R. (2021). High-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator. En 2021 IEEE 12th Latin American Symposium on Circuits and Systems, LASCAS 2021 Artículo 9459151 (2021 IEEE 12th Latin American Symposium on Circuits and Systems, LASCAS 2021). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/LASCAS51355.2021.9459151

Escobar, Ricardo ; Procel, Luis Miguel ; Trojman, Lionel et al. / High-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator. 2021 IEEE 12th Latin American Symposium on Circuits and Systems, LASCAS 2021. Institute of Electrical and Electronics Engineers Inc., 2021. (2021 IEEE 12th Latin American Symposium on Circuits and Systems, LASCAS 2021).

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title = "High-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator",

abstract = "This paper presents an energy-efficient single-clock-cycle binary Dual-Mode Logic (DML)-based comparator optimized to operate in the dynamic mode. The parallel-prefix architecture is implemented to ensure high speed, whereas low power consumption is guaranteed by reducing the switching activities of internal nodes. Domino Logic (DL) and DML implementations are compared in terms of delay and energy for different supply voltages in the 32 nm technology. We demonstrate an average improvement of 5\% in both energy and delay when the DML design is operating in the dynamic mode compared to its conventional domino counterpart. Moreover, the DML design operating in the static mode allows to save up to 43\% energy consumption compared to the equivalent domino logic-based implementation.",

keywords = "CMOS, Dual-mode logic, arithmetic circuits, binary comparator",

author = "Ricardo Escobar and Procel, \{Luis Miguel\} and Lionel Trojman and Marco Lanuzza and Ramiro Taco",

note = "Publisher Copyright: {\textcopyright} 2021 IEEE.; 12th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2021 ; Conference date: 22-02-2021 Through 25-02-2021",

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Escobar, R, Procel, LM, Trojman, L, Lanuzza, M & Taco, R 2021, High-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator. En 2021 IEEE 12th Latin American Symposium on Circuits and Systems, LASCAS 2021., 9459151, 2021 IEEE 12th Latin American Symposium on Circuits and Systems, LASCAS 2021, Institute of Electrical and Electronics Engineers Inc., 12th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2021, Arequipa, Perú, 22/02/21. https://doi.org/10.1109/LASCAS51355.2021.9459151

High-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator. / Escobar, Ricardo; Procel, Luis Miguel; Trojman, Lionel et al.
2021 IEEE 12th Latin American Symposium on Circuits and Systems, LASCAS 2021. Institute of Electrical and Electronics Engineers Inc., 2021. 9459151 (2021 IEEE 12th Latin American Symposium on Circuits and Systems, LASCAS 2021).

Producción científica: Capítulo del libro/informe/acta de congreso › Contribución a la conferencia › revisión exhaustiva

TY - GEN

T1 - High-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator

AU - Escobar, Ricardo

AU - Procel, Luis Miguel

AU - Trojman, Lionel

AU - Lanuzza, Marco

AU - Taco, Ramiro

PY - 2021/2/21

Y1 - 2021/2/21

N2 - This paper presents an energy-efficient single-clock-cycle binary Dual-Mode Logic (DML)-based comparator optimized to operate in the dynamic mode. The parallel-prefix architecture is implemented to ensure high speed, whereas low power consumption is guaranteed by reducing the switching activities of internal nodes. Domino Logic (DL) and DML implementations are compared in terms of delay and energy for different supply voltages in the 32 nm technology. We demonstrate an average improvement of 5% in both energy and delay when the DML design is operating in the dynamic mode compared to its conventional domino counterpart. Moreover, the DML design operating in the static mode allows to save up to 43% energy consumption compared to the equivalent domino logic-based implementation.

AB - This paper presents an energy-efficient single-clock-cycle binary Dual-Mode Logic (DML)-based comparator optimized to operate in the dynamic mode. The parallel-prefix architecture is implemented to ensure high speed, whereas low power consumption is guaranteed by reducing the switching activities of internal nodes. Domino Logic (DL) and DML implementations are compared in terms of delay and energy for different supply voltages in the 32 nm technology. We demonstrate an average improvement of 5% in both energy and delay when the DML design is operating in the dynamic mode compared to its conventional domino counterpart. Moreover, the DML design operating in the static mode allows to save up to 43% energy consumption compared to the equivalent domino logic-based implementation.

KW - CMOS

KW - Dual-mode logic

KW - arithmetic circuits

KW - binary comparator

UR - https://www.scopus.com/pages/publications/85113967263

U2 - 10.1109/LASCAS51355.2021.9459151

DO - 10.1109/LASCAS51355.2021.9459151

M3 - Contribución a la conferencia

AN - SCOPUS:85113967263

T3 - 2021 IEEE 12th Latin American Symposium on Circuits and Systems, LASCAS 2021

BT - 2021 IEEE 12th Latin American Symposium on Circuits and Systems, LASCAS 2021

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 12th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2021

Y2 - 22 February 2021 through 25 February 2021

ER -

Escobar R, Procel LM, Trojman L, Lanuzza M, Taco R. High-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator. En 2021 IEEE 12th Latin American Symposium on Circuits and Systems, LASCAS 2021. Institute of Electrical and Electronics Engineers Inc. 2021. 9459151. (2021 IEEE 12th Latin American Symposium on Circuits and Systems, LASCAS 2021). doi: 10.1109/LASCAS51355.2021.9459151

High-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator

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