Improving speed and power characteristics of pulse-triggered flip-flops

Marco Lanuzza, Ramiro Taco

Producción científica: Capítulo del libro/informe/acta de congresoContribución a la conferenciarevisión exhaustiva

2 Citas (Scopus)

Resumen

This paper presents a simple circuital technique to design efficient pulse triggered flip-flops. The proposed approach aims at considerably alleviating the detrimental effects of current contention mechanisms, occurring at critical switching nodes during an output switching. In this way, both latency and power consumption are reduced. The proposed approach is assessed by means of simulations in 90-nm ST commercial CMOS technology. When applied to some recently proposed implicit pulse triggered flip-flop architectures, the suggested design strategy, allows speed to be improved up to 13% and power-delay-product to be lowered down to 14%. Moreover, also the process variation tolerance is considerably improved.

Idioma originalInglés
Título de la publicación alojada2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Conference Proceedings
EditorialIEEE Computer Society
ISBN (versión impresa)9781479925070
DOI
EstadoPublicada - 2014
Publicado de forma externa
Evento2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Santiago, Chile
Duración: 25 feb. 201428 feb. 2014

Serie de la publicación

Nombre2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Conference Proceedings

Conferencia

Conferencia2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014
País/TerritorioChile
CiudadSantiago
Período25/02/1428/02/14

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