TY - GEN
T1 - Live Demo
T2 - 53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021
AU - Stanger, Inbal
AU - Shavit, Netanel
AU - Taco, Ramiro
AU - Lanuzza, Marco
AU - Fish, Alexander
N1 - Publisher Copyright:
© 2021 IEEE
PY - 2021
Y1 - 2021
N2 - This demo demonstrates the unique capabilities of the multimode Dual Mode Logic (DML) design technique to define run-time adaptive datapaths to overcome process and environmental (i.e., temperature and voltage) variations. A proof-of concept benchmark circuit is designed and fabricated in 65 nm technology. Measurements on 10 test chips, while considering supply voltages spanning 0.6V to 1.2V and temperature variations ranging from − 40 ° C to 125 ° C confirmed the effectiveness of the proposed approach to compensate even for severe process, voltage and temperature (PVT) variations.
AB - This demo demonstrates the unique capabilities of the multimode Dual Mode Logic (DML) design technique to define run-time adaptive datapaths to overcome process and environmental (i.e., temperature and voltage) variations. A proof-of concept benchmark circuit is designed and fabricated in 65 nm technology. Measurements on 10 test chips, while considering supply voltages spanning 0.6V to 1.2V and temperature variations ranging from − 40 ° C to 125 ° C confirmed the effectiveness of the proposed approach to compensate even for severe process, voltage and temperature (PVT) variations.
UR - http://www.scopus.com/inward/record.url?scp=85108989791&partnerID=8YFLogxK
U2 - 10.1109/ISCAS51556.2021.9401425
DO - 10.1109/ISCAS51556.2021.9401425
M3 - Contribución a la conferencia
AN - SCOPUS:85108989791
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
BT - 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 22 May 2021 through 28 May 2021
ER -