Live demonstration: A 0.8V, 1.54 pJ / 940 MHz dual mode logic-based 16x16-bit booth multiplier in 16-nm FinFET

Netanel Shavit; Inbal Stanger; Ramiro Taco; Marco Lanuzza; Alexander Fish

doi:10.1109/ISCAS51556.2021.9401241

Live demonstration: A 0.8V, 1.54 pJ / 940 MHz dual mode logic-based 16x16-bit booth multiplier in 16-nm FinFET

Netanel Shavit, Inbal Stanger, Ramiro Taco, Marco Lanuzza, Alexander Fish

Ingeniería Electrónica y Automatización

Producción científica: Capítulo del libro/informe/acta de congreso › Contribución a la conferencia › revisión exhaustiva

Resumen

The Dual Mode Logic (DML) defines run-time adaptive digital architectures that switch to either improved performance or lower energy consumption as a function of actual computational workload. This flexibility is demonstrated for the first time by silicon measurements on a 16x16-bit Booth multiplier fabricated as a part of an ultra-low power digital signal processing (DSP) architecture for 16-nm FinFET technology. When running in the full-speed mode, the DML multiplier can achieve a performance boost of 19.5% as compared to the equivalent standard CMOS design. The same design saves precious energy (-27%, on average) when the energy-efficient mode is enabled, while occupying 13% less silicon area.

Idioma original	Inglés
Título de la publicación alojada	2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings
Editorial	Institute of Electrical and Electronics Engineers Inc.
ISBN (versión digital)	9781728192017
DOI	https://doi.org/10.1109/ISCAS51556.2021.9401241
Estado	Publicada - 2021
Evento	53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Daegu, República de Corea Duración: 22 may. 2021 → 28 may. 2021

Serie de la publicación

Nombre	Proceedings - IEEE International Symposium on Circuits and Systems
Volumen	2021-May
ISSN (versión impresa)	0271-4310

Conferencia

Conferencia	53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021
País/Territorio	República de Corea
Ciudad	Daegu
Período	22/05/21 → 28/05/21

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10.1109/ISCAS51556.2021.9401241

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Shavit, N., Stanger, I., Taco, R., Lanuzza, M., & Fish, A. (2021). Live demonstration: A 0.8V, 1.54 pJ / 940 MHz dual mode logic-based 16x16-bit booth multiplier in 16-nm FinFET. En 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings Artículo 9401241 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2021-May). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS51556.2021.9401241

Shavit, Netanel ; Stanger, Inbal ; Taco, Ramiro et al. / Live demonstration : A 0.8V, 1.54 pJ / 940 MHz dual mode logic-based 16x16-bit booth multiplier in 16-nm FinFET. 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2021. (Proceedings - IEEE International Symposium on Circuits and Systems).

@inproceedings{0fd62cd174264e728f2ac3a57b9de10f,

title = "Live demonstration: A 0.8V, 1.54 pJ / 940 MHz dual mode logic-based 16x16-bit booth multiplier in 16-nm FinFET",

abstract = "The Dual Mode Logic (DML) defines run-time adaptive digital architectures that switch to either improved performance or lower energy consumption as a function of actual computational workload. This flexibility is demonstrated for the first time by silicon measurements on a 16x16-bit Booth multiplier fabricated as a part of an ultra-low power digital signal processing (DSP) architecture for 16-nm FinFET technology. When running in the full-speed mode, the DML multiplier can achieve a performance boost of 19.5% as compared to the equivalent standard CMOS design. The same design saves precious energy (-27%, on average) when the energy-efficient mode is enabled, while occupying 13% less silicon area.",

author = "Netanel Shavit and Inbal Stanger and Ramiro Taco and Marco Lanuzza and Alexander Fish",

note = "Publisher Copyright: {\textcopyright} 2021 IEEE; 53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021 ; Conference date: 22-05-2021 Through 28-05-2021",

year = "2021",

doi = "10.1109/ISCAS51556.2021.9401241",

language = "Ingl{\'e}s",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings",

}

Shavit, N, Stanger, I, Taco, R, Lanuzza, M & Fish, A 2021, Live demonstration: A 0.8V, 1.54 pJ / 940 MHz dual mode logic-based 16x16-bit booth multiplier in 16-nm FinFET. En 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings., 9401241, Proceedings - IEEE International Symposium on Circuits and Systems, vol. 2021-May, Institute of Electrical and Electronics Engineers Inc., 53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021, Daegu, República de Corea, 22/05/21. https://doi.org/10.1109/ISCAS51556.2021.9401241

Live demonstration: A 0.8V, 1.54 pJ / 940 MHz dual mode logic-based 16x16-bit booth multiplier in 16-nm FinFET. / Shavit, Netanel; Stanger, Inbal; Taco, Ramiro et al.
2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2021. 9401241 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2021-May).

Producción científica: Capítulo del libro/informe/acta de congreso › Contribución a la conferencia › revisión exhaustiva

TY - GEN

T1 - Live demonstration

T2 - 53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021

AU - Shavit, Netanel

AU - Stanger, Inbal

AU - Taco, Ramiro

AU - Lanuzza, Marco

AU - Fish, Alexander

PY - 2021

Y1 - 2021

N2 - The Dual Mode Logic (DML) defines run-time adaptive digital architectures that switch to either improved performance or lower energy consumption as a function of actual computational workload. This flexibility is demonstrated for the first time by silicon measurements on a 16x16-bit Booth multiplier fabricated as a part of an ultra-low power digital signal processing (DSP) architecture for 16-nm FinFET technology. When running in the full-speed mode, the DML multiplier can achieve a performance boost of 19.5% as compared to the equivalent standard CMOS design. The same design saves precious energy (-27%, on average) when the energy-efficient mode is enabled, while occupying 13% less silicon area.

AB - The Dual Mode Logic (DML) defines run-time adaptive digital architectures that switch to either improved performance or lower energy consumption as a function of actual computational workload. This flexibility is demonstrated for the first time by silicon measurements on a 16x16-bit Booth multiplier fabricated as a part of an ultra-low power digital signal processing (DSP) architecture for 16-nm FinFET technology. When running in the full-speed mode, the DML multiplier can achieve a performance boost of 19.5% as compared to the equivalent standard CMOS design. The same design saves precious energy (-27%, on average) when the energy-efficient mode is enabled, while occupying 13% less silicon area.

UR - http://www.scopus.com/inward/record.url?scp=85109003902&partnerID=8YFLogxK

U2 - 10.1109/ISCAS51556.2021.9401241

DO - 10.1109/ISCAS51556.2021.9401241

M3 - Contribución a la conferencia

AN - SCOPUS:85109003902

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

BT - 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

Y2 - 22 May 2021 through 28 May 2021

ER -

Shavit N, Stanger I, Taco R, Lanuzza M, Fish A. Live demonstration: A 0.8V, 1.54 pJ / 940 MHz dual mode logic-based 16x16-bit booth multiplier in 16-nm FinFET. En 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2021. 9401241. (Proceedings - IEEE International Symposium on Circuits and Systems). doi: 10.1109/ISCAS51556.2021.9401241

Live demonstration: A 0.8V, 1.54 pJ / 940 MHz dual mode logic-based 16x16-bit booth multiplier in 16-nm FinFET

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