Low voltage ripple carry adder with low-granularity dynamic forward back-biasing in 28 nm UTBB FD-SOI

Ramiro Taco, Itamar Levi, Marco Lanuzza, Alexander Fish

Producción científica: Capítulo del libro/informe/acta de congresoContribución a la conferenciarevisión exhaustiva

2 Citas (Scopus)

Resumen

In this paper, a low voltage ripple-carry adder (RCA), designed for the ultra-thin body and box (UTBB) fully-depleted silicon-on-insulator (FD-SOI) technology, is proposed. The circuit synergistically benefits from low-granularity back-bias control to improve performance in conjunction with the integration of both NMOS and PMOS devices into a common well configuration which allows highly efficient area utilization. The design was compared over standard CMOS and DTMOS solutions. Comparative post-layout results demonstrate that the suggested approach improves energy consumption up to 57% in comparison to the equivalent DTMOS design and reduces delay up to 30% with similar energy consumption, when compared to the conventional CMOS implementation. In addition, reduced silicon area occupancy is achieved.

Idioma originalInglés
Título de la publicación alojada2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015
EditorialInstitute of Electrical and Electronics Engineers Inc.
ISBN (versión digital)9781509002597
DOI
EstadoPublicada - 20 nov. 2015
Publicado de forma externa
EventoIEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015 - Rohnert Park, Estados Unidos
Duración: 5 oct. 20158 oct. 2015

Serie de la publicación

Nombre2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015

Conferencia

ConferenciaIEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015
País/TerritorioEstados Unidos
CiudadRohnert Park
Período5/10/158/10/15

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