TY - GEN
T1 - MTJ-Based NV-BCAM Design with Dual Voltage Level Control Circuitry
AU - Caisaluisa, Oliver
AU - Holguin, Eduardo
AU - Procel, Luis Miguel
N1 - Publisher Copyright:
© 2025 IEEE.
PY - 2025
Y1 - 2025
N2 - Non-volatile emerging technologies exploiting magnetic tunnel junction (MTJ) capabilities are presented as promising alternatives to conventional Content Addressable Memories (CAMs). In this paper, an eight-transistor-two-MTJ (8T2MTJ) NV Binary CAM based on a voltage-divider configuration is proposed along with a Dual Voltage Level Control Circuitry (DVLCC) and periphery design to drive search and write control signals through the Searchline. The design was evaluated under nominal, as well as mismatch and process variation through 1000 Monte Carlo simulations for write and search delay, energy, search error rate (SER), and search stability margins. In particular, compared to state-of-the-art designs, the proposed 144-bit NV-BCAM offers lower (1.8%) SER, at the expense of a slight increase in search delay and search energy per bit. However, our design offers DVLCC which allows combined search and write operations through a single VDD supply.
AB - Non-volatile emerging technologies exploiting magnetic tunnel junction (MTJ) capabilities are presented as promising alternatives to conventional Content Addressable Memories (CAMs). In this paper, an eight-transistor-two-MTJ (8T2MTJ) NV Binary CAM based on a voltage-divider configuration is proposed along with a Dual Voltage Level Control Circuitry (DVLCC) and periphery design to drive search and write control signals through the Searchline. The design was evaluated under nominal, as well as mismatch and process variation through 1000 Monte Carlo simulations for write and search delay, energy, search error rate (SER), and search stability margins. In particular, compared to state-of-the-art designs, the proposed 144-bit NV-BCAM offers lower (1.8%) SER, at the expense of a slight increase in search delay and search energy per bit. However, our design offers DVLCC which allows combined search and write operations through a single VDD supply.
KW - BCAM
KW - binary CAM
KW - CAM
KW - content-addressable memory
KW - DMTJ
KW - magnetic tunnel junction
KW - MTJ
UR - http://www.scopus.com/inward/record.url?scp=105004551329&partnerID=8YFLogxK
U2 - 10.1109/LASCAS64004.2025.10966331
DO - 10.1109/LASCAS64004.2025.10966331
M3 - Contribución a la conferencia
AN - SCOPUS:105004551329
T3 - 2025 IEEE 16th Latin American Symposium on Circuits and Systems, LASCAS 2025 - Proceedings
BT - 2025 IEEE 16th Latin American Symposium on Circuits and Systems, LASCAS 2025 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 16th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2025
Y2 - 25 February 2025 through 28 February 2025
ER -