MTJ-Based NV-BCAM Design with Dual Voltage Level Control Circuitry

Oliver Caisaluisa, Eduardo Holguin, Luis Miguel Procel

Producción científica: Capítulo del libro/informe/acta de congresoContribución a la conferenciarevisión exhaustiva

Resumen

Non-volatile emerging technologies exploiting magnetic tunnel junction (MTJ) capabilities are presented as promising alternatives to conventional Content Addressable Memories (CAMs). In this paper, an eight-transistor-two-MTJ (8T2MTJ) NV Binary CAM based on a voltage-divider configuration is proposed along with a Dual Voltage Level Control Circuitry (DVLCC) and periphery design to drive search and write control signals through the Searchline. The design was evaluated under nominal, as well as mismatch and process variation through 1000 Monte Carlo simulations for write and search delay, energy, search error rate (SER), and search stability margins. In particular, compared to state-of-the-art designs, the proposed 144-bit NV-BCAM offers lower (1.8%) SER, at the expense of a slight increase in search delay and search energy per bit. However, our design offers DVLCC which allows combined search and write operations through a single VDD supply.

Idioma originalInglés
Título de la publicación alojada2025 IEEE 16th Latin American Symposium on Circuits and Systems, LASCAS 2025 - Proceedings
EditorialInstitute of Electrical and Electronics Engineers Inc.
ISBN (versión digital)9798331522124
DOI
EstadoPublicada - 2025
Evento16th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2025 - Bento Goncalves, Brasil
Duración: 25 feb. 202528 feb. 2025

Serie de la publicación

Nombre2025 IEEE 16th Latin American Symposium on Circuits and Systems, LASCAS 2025 - Proceedings

Conferencia

Conferencia16th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2025
País/TerritorioBrasil
CiudadBento Goncalves
Período25/02/2528/02/25

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