Performance Benchmarking of FinFET- and TFET-Based STT-MRAM Bitcells Operating at Ultra-Low Voltages

Santiago S. Pérez; Alessandro Bedoya; Luis Miguel Prócel; Ramiro Taco

doi:10.1109/lascas56464.2023.10108163

Performance Benchmarking of FinFET- and TFET-Based STT-MRAM Bitcells Operating at Ultra-Low Voltages

Santiago S. Pérez, Alessandro Bedoya, Luis Miguel Prócel, Ramiro Taco

Universidad San Francisco de Quito

Producción científica: Capítulo del libro/informe/acta de congreso › Contribución a la conferencia › revisión exhaustiva

Resumen

STT-MRAMs have emerged as the leading candidate of on-chip technology for nonvolatile cache applications. In this paper, DMTJs are used to build STT-MRAMs at the circuit level with a reduced switching current benchmarking the TFET technology model and a calibrated 10nm-FinFET technology model to explore the best configuration in the ultralow voltage domain for writing operation in terms of energy-efficiency and area. Simulation results showed that the TFET-based solutions are the most energy-efficiency in terms of the EDP index with an average EDP 57.77% lower than the FinFET-based configurations. TFET-based bitcells had a 40.23% smaller delay and 34.11% less writing energy compared to the FinFET counterparts. Finally, a standby power analysis was carried out.

Idioma original	Inglés
Título de la publicación alojada	LASCAS 2023 - 14th IEEE Latin American Symposium on Circuits and Systems, Proceedings
Editores	Monica Karel Huerta
Editorial	Institute of Electrical and Electronics Engineers Inc.
ISBN (versión digital)	9781665457057
DOI	https://doi.org/10.1109/lascas56464.2023.10108163
Estado	Publicada - 2023
Evento	14th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2023 - Quito, Ecuador Duración: 27 feb. 2023 → 3 mar. 2023

Serie de la publicación

Nombre	2023 IEEE 14th Latin America Symposium on Circuits and Systems (LASCAS)

Conferencia

Conferencia	14th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2023
País/Territorio	Ecuador
Ciudad	Quito
Período	27/02/23 → 3/03/23

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10.1109/lascas56464.2023.10108163

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Pérez, S. S., Bedoya, A., Prócel, L. M., & Taco, R. (2023). Performance Benchmarking of FinFET- and TFET-Based STT-MRAM Bitcells Operating at Ultra-Low Voltages. En M. K. Huerta (Ed.), LASCAS 2023 - 14th IEEE Latin American Symposium on Circuits and Systems, Proceedings (2023 IEEE 14th Latin America Symposium on Circuits and Systems (LASCAS)). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/lascas56464.2023.10108163

Pérez, Santiago S. ; Bedoya, Alessandro ; Prócel, Luis Miguel et al. / Performance Benchmarking of FinFET- and TFET-Based STT-MRAM Bitcells Operating at Ultra-Low Voltages. LASCAS 2023 - 14th IEEE Latin American Symposium on Circuits and Systems, Proceedings. editor / Monica Karel Huerta. Institute of Electrical and Electronics Engineers Inc., 2023. (2023 IEEE 14th Latin America Symposium on Circuits and Systems (LASCAS)).

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title = "Performance Benchmarking of FinFET- and TFET-Based STT-MRAM Bitcells Operating at Ultra-Low Voltages",

abstract = "STT-MRAMs have emerged as the leading candidate of on-chip technology for nonvolatile cache applications. In this paper, DMTJs are used to build STT-MRAMs at the circuit level with a reduced switching current benchmarking the TFET technology model and a calibrated 10nm-FinFET technology model to explore the best configuration in the ultralow voltage domain for writing operation in terms of energy-efficiency and area. Simulation results showed that the TFET-based solutions are the most energy-efficiency in terms of the EDP index with an average EDP 57.77% lower than the FinFET-based configurations. TFET-based bitcells had a 40.23% smaller delay and 34.11% less writing energy compared to the FinFET counterparts. Finally, a standby power analysis was carried out.",

keywords = "DMTJ, Fin-FET, MTJ, Magnetic Tunnel Junction, STT-MRAM, Spintronics, TFET, Tunnel FET, leakage current",

author = "P{\'e}rez, {Santiago S.} and Alessandro Bedoya and Pr{\'o}cel, {Luis Miguel} and Ramiro Taco",

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year = "2023",

doi = "10.1109/lascas56464.2023.10108163",

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series = "2023 IEEE 14th Latin America Symposium on Circuits and Systems (LASCAS)",

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Pérez, SS, Bedoya, A, Prócel, LM & Taco, R 2023, Performance Benchmarking of FinFET- and TFET-Based STT-MRAM Bitcells Operating at Ultra-Low Voltages. En MK Huerta (ed.), LASCAS 2023 - 14th IEEE Latin American Symposium on Circuits and Systems, Proceedings. 2023 IEEE 14th Latin America Symposium on Circuits and Systems (LASCAS), Institute of Electrical and Electronics Engineers Inc., 14th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2023, Quito, Ecuador, 27/02/23. https://doi.org/10.1109/lascas56464.2023.10108163

Performance Benchmarking of FinFET- and TFET-Based STT-MRAM Bitcells Operating at Ultra-Low Voltages. / Pérez, Santiago S.; Bedoya, Alessandro; Prócel, Luis Miguel et al.
LASCAS 2023 - 14th IEEE Latin American Symposium on Circuits and Systems, Proceedings. ed. / Monica Karel Huerta. Institute of Electrical and Electronics Engineers Inc., 2023. (2023 IEEE 14th Latin America Symposium on Circuits and Systems (LASCAS)).

Producción científica: Capítulo del libro/informe/acta de congreso › Contribución a la conferencia › revisión exhaustiva

TY - GEN

T1 - Performance Benchmarking of FinFET- and TFET-Based STT-MRAM Bitcells Operating at Ultra-Low Voltages

AU - Pérez, Santiago S.

AU - Bedoya, Alessandro

AU - Prócel, Luis Miguel

AU - Taco, Ramiro

PY - 2023

Y1 - 2023

N2 - STT-MRAMs have emerged as the leading candidate of on-chip technology for nonvolatile cache applications. In this paper, DMTJs are used to build STT-MRAMs at the circuit level with a reduced switching current benchmarking the TFET technology model and a calibrated 10nm-FinFET technology model to explore the best configuration in the ultralow voltage domain for writing operation in terms of energy-efficiency and area. Simulation results showed that the TFET-based solutions are the most energy-efficiency in terms of the EDP index with an average EDP 57.77% lower than the FinFET-based configurations. TFET-based bitcells had a 40.23% smaller delay and 34.11% less writing energy compared to the FinFET counterparts. Finally, a standby power analysis was carried out.

AB - STT-MRAMs have emerged as the leading candidate of on-chip technology for nonvolatile cache applications. In this paper, DMTJs are used to build STT-MRAMs at the circuit level with a reduced switching current benchmarking the TFET technology model and a calibrated 10nm-FinFET technology model to explore the best configuration in the ultralow voltage domain for writing operation in terms of energy-efficiency and area. Simulation results showed that the TFET-based solutions are the most energy-efficiency in terms of the EDP index with an average EDP 57.77% lower than the FinFET-based configurations. TFET-based bitcells had a 40.23% smaller delay and 34.11% less writing energy compared to the FinFET counterparts. Finally, a standby power analysis was carried out.

KW - DMTJ

KW - Fin-FET

KW - MTJ

KW - Magnetic Tunnel Junction

KW - STT-MRAM

KW - Spintronics

KW - TFET

KW - Tunnel FET

KW - leakage current

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M3 - Contribución a la conferencia

AN - SCOPUS:85159660176

T3 - 2023 IEEE 14th Latin America Symposium on Circuits and Systems (LASCAS)

BT - LASCAS 2023 - 14th IEEE Latin American Symposium on Circuits and Systems, Proceedings

A2 - Huerta, Monica Karel

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 14th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2023

Y2 - 27 February 2023 through 3 March 2023

ER -

Pérez SS, Bedoya A, Prócel LM, Taco R. Performance Benchmarking of FinFET- and TFET-Based STT-MRAM Bitcells Operating at Ultra-Low Voltages. En Huerta MK, editor, LASCAS 2023 - 14th IEEE Latin American Symposium on Circuits and Systems, Proceedings. Institute of Electrical and Electronics Engineers Inc. 2023. (2023 IEEE 14th Latin America Symposium on Circuits and Systems (LASCAS)). doi: 10.1109/lascas56464.2023.10108163

Performance Benchmarking of FinFET- and TFET-Based STT-MRAM Bitcells Operating at Ultra-Low Voltages

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