Power and Area Reduction of MD5 based on Cryptoprocessor Using novel approach of Internal Counters on the Finite State Machine

Juan Jose Jimenez, Lionel Trojman, Luis Miguel Procel

Producción científica: Capítulo del libro/informe/acta de congresoContribución a la conferenciarevisión exhaustiva

4 Citas (Scopus)

Resumen

This work presents the design of a very simple microprocessor dedicated to cryptographic operations implementing Message Digest Algorithm 5 (MD5). We tested two control types based on the Moore Finite State Machine: with and without registers as counters. The design was performed with Synopsys TCAD using an open source 500nm technology iPDK. The design using FSM with registers as internal counter results a reduction of 13% on the Silicon area and the simulation demonstrates that we could reach a reduction of 22% of power consumption explained by an 8% decrease of cells required for encryption operations.

Idioma originalInglés
Título de la publicación alojada2019 IEEE 4th Ecuador Technical Chapters Meeting, ETCM 2019
EditorialInstitute of Electrical and Electronics Engineers Inc.
ISBN (versión digital)9781728137643
DOI
EstadoPublicada - nov. 2019
Evento4th IEEE Ecuador Technical Chapters Meeting, ETCM 2019 - Guayaquil, Ecuador
Duración: 13 nov. 201915 nov. 2019

Serie de la publicación

Nombre2019 IEEE 4th Ecuador Technical Chapters Meeting, ETCM 2019

Conferencia

Conferencia4th IEEE Ecuador Technical Chapters Meeting, ETCM 2019
País/TerritorioEcuador
CiudadGuayaquil
Período13/11/1915/11/19

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