TY - GEN
T1 - Reconfigurable CMOS/STT-MTJ Non-Volatile Circuit for Logic-in-Memory Applications
AU - Garzon, Esteban
AU - Zambrano, Benjamin
AU - Moposita, Tatiana
AU - Taco, Ramiro
AU - Procel, Luis Miguel
AU - Trojman, Lionel
N1 - Publisher Copyright:
© 2020 IEEE.
PY - 2020/2
Y1 - 2020/2
N2 - The unique properties of spin-transfer torque magnetic tunnel junctions (STT-MTJs) have led to promising designs for logic and memory applications. Additionally, STT-MTJ based circuits have shown attractive potential to design efficient non-volatile logic-in-memory (NV-LIM) architectures, which assure low power and increased speed. This paper proposes a bit-level reconfigurable NV logic circuit based on hybrid CMOS/STT-MTJ design. Indeed, our circuit can adapt on-demand its structure, thus offering intrinsic flexibility to perform basic logic functions (i.e. AND/OR/XOR) by a single circuit architecture. Post-layout simulation results prove that the proposed circuit leads to increase both delay and energy consumption with respect to state-of-the-art non-reconfigurable designs. However, its reconfigurable operation capability is very attractive to reduce area occupation and to increase design flexibility of NV-LIM systems.
AB - The unique properties of spin-transfer torque magnetic tunnel junctions (STT-MTJs) have led to promising designs for logic and memory applications. Additionally, STT-MTJ based circuits have shown attractive potential to design efficient non-volatile logic-in-memory (NV-LIM) architectures, which assure low power and increased speed. This paper proposes a bit-level reconfigurable NV logic circuit based on hybrid CMOS/STT-MTJ design. Indeed, our circuit can adapt on-demand its structure, thus offering intrinsic flexibility to perform basic logic functions (i.e. AND/OR/XOR) by a single circuit architecture. Post-layout simulation results prove that the proposed circuit leads to increase both delay and energy consumption with respect to state-of-the-art non-reconfigurable designs. However, its reconfigurable operation capability is very attractive to reduce area occupation and to increase design flexibility of NV-LIM systems.
KW - Magnetic tunnel junction (MTJ)
KW - logic-in-memory (LIM)
KW - non-volatile logic gates
KW - spin-transfer torque (STT)
UR - http://www.scopus.com/inward/record.url?scp=85084322434&partnerID=8YFLogxK
U2 - 10.1109/LASCAS45839.2020.9069027
DO - 10.1109/LASCAS45839.2020.9069027
M3 - Contribución a la conferencia
AN - SCOPUS:85084322434
T3 - 2020 IEEE 11th Latin American Symposium on Circuits and Systems, LASCAS 2020
BT - 2020 IEEE 11th Latin American Symposium on Circuits and Systems, LASCAS 2020
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 11th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2020
Y2 - 25 February 2020 through 28 February 2020
ER -