Reconfigurable CMOS/STT-MTJ Non-Volatile Circuit for Logic-in-Memory Applications

Esteban Garzon, Benjamin Zambrano, Tatiana Moposita, Ramiro Taco, Luis Miguel Procel, Lionel Trojman

Producción científica: Capítulo del libro/informe/acta de congresoContribución a la conferenciarevisión exhaustiva

15 Citas (Scopus)

Resumen

The unique properties of spin-transfer torque magnetic tunnel junctions (STT-MTJs) have led to promising designs for logic and memory applications. Additionally, STT-MTJ based circuits have shown attractive potential to design efficient non-volatile logic-in-memory (NV-LIM) architectures, which assure low power and increased speed. This paper proposes a bit-level reconfigurable NV logic circuit based on hybrid CMOS/STT-MTJ design. Indeed, our circuit can adapt on-demand its structure, thus offering intrinsic flexibility to perform basic logic functions (i.e. AND/OR/XOR) by a single circuit architecture. Post-layout simulation results prove that the proposed circuit leads to increase both delay and energy consumption with respect to state-of-the-art non-reconfigurable designs. However, its reconfigurable operation capability is very attractive to reduce area occupation and to increase design flexibility of NV-LIM systems.

Idioma originalInglés
Título de la publicación alojada2020 IEEE 11th Latin American Symposium on Circuits and Systems, LASCAS 2020
EditorialInstitute of Electrical and Electronics Engineers Inc.
ISBN (versión digital)9781728134277
DOI
EstadoPublicada - feb. 2020
Evento11th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2020 - San Jose, Costa Rica
Duración: 25 feb. 202028 feb. 2020

Serie de la publicación

Nombre2020 IEEE 11th Latin American Symposium on Circuits and Systems, LASCAS 2020

Conferencia

Conferencia11th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2020
País/TerritorioCosta Rica
CiudadSan Jose
Período25/02/2028/02/20

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