TY - JOUR
T1 - Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths
AU - Stanger, Inbal
AU - Shavit, Netanel
AU - Taco, Ramiro
AU - Lanuzza, Marco
AU - Fish, Alexander
N1 - Publisher Copyright:
© 2004-2012 IEEE.
PY - 2020/9
Y1 - 2020/9
N2 - This brief presents the unique capabilities of the multimode Dual Mode Logic (DML) design technique to define run-time adaptive datapaths to overcome process and environmental (i.e., temperature and voltage) variations. A proof-of-concept benchmark circuit is designed and fabricated in 65 nm technology. Measurements on 10 test chips, while considering supply voltages spanning 0.6V to 1.2V and temperature variations ranging from -40 °C to 125 °C confirm the effectiveness of this approach to compensate for severe process, voltage and temperature (PVT) variations.
AB - This brief presents the unique capabilities of the multimode Dual Mode Logic (DML) design technique to define run-time adaptive datapaths to overcome process and environmental (i.e., temperature and voltage) variations. A proof-of-concept benchmark circuit is designed and fabricated in 65 nm technology. Measurements on 10 test chips, while considering supply voltages spanning 0.6V to 1.2V and temperature variations ranging from -40 °C to 125 °C confirm the effectiveness of this approach to compensate for severe process, voltage and temperature (PVT) variations.
KW - Dual mode logic (DML)
KW - PVT variation tolerance
KW - adaptive circuits
UR - http://www.scopus.com/inward/record.url?scp=85090857156&partnerID=8YFLogxK
U2 - 10.1109/TCSII.2020.3013331
DO - 10.1109/TCSII.2020.3013331
M3 - Artículo
AN - SCOPUS:85090857156
SN - 1549-7747
VL - 67
SP - 1639
EP - 1643
JO - IEEE Transactions on Circuits and Systems II: Express Briefs
JF - IEEE Transactions on Circuits and Systems II: Express Briefs
IS - 9
M1 - 9153856
ER -