Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths

Inbal Stanger, Netanel Shavit, Ramiro Taco, Marco Lanuzza, Alexander Fish

Producción científica: Contribución a una revistaArtículorevisión exhaustiva

9 Citas (Scopus)

Resumen

This brief presents the unique capabilities of the multimode Dual Mode Logic (DML) design technique to define run-time adaptive datapaths to overcome process and environmental (i.e., temperature and voltage) variations. A proof-of-concept benchmark circuit is designed and fabricated in 65 nm technology. Measurements on 10 test chips, while considering supply voltages spanning 0.6V to 1.2V and temperature variations ranging from -40 °C to 125 °C confirm the effectiveness of this approach to compensate for severe process, voltage and temperature (PVT) variations.

Idioma originalInglés
Número de artículo9153856
Páginas (desde-hasta)1639-1643
Número de páginas5
PublicaciónIEEE Transactions on Circuits and Systems II: Express Briefs
Volumen67
N.º9
DOI
EstadoPublicada - sep. 2020

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