Resumen
This brief presents the unique capabilities of the multimode Dual Mode Logic (DML) design technique to define run-time adaptive datapaths to overcome process and environmental (i.e., temperature and voltage) variations. A proof-of-concept benchmark circuit is designed and fabricated in 65 nm technology. Measurements on 10 test chips, while considering supply voltages spanning 0.6V to 1.2V and temperature variations ranging from -40 °C to 125 °C confirm the effectiveness of this approach to compensate for severe process, voltage and temperature (PVT) variations.
| Idioma original | Inglés |
|---|---|
| Número de artículo | 9153856 |
| Páginas (desde-hasta) | 1639-1643 |
| Número de páginas | 5 |
| Publicación | IEEE Transactions on Circuits and Systems II: Express Briefs |
| Volumen | 67 |
| N.º | 9 |
| DOI | |
| Estado | Publicada - sep. 2020 |
Huella
Profundice en los temas de investigación de 'Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths'. En conjunto forman una huella única.Citar esto
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