Trapping in 1nm EOT high-k/mg

M. B. Zahid, L. Pantisano, R. Degraeve, M. Aoulaiche, L. Trojman, I. Ferain, E. San Andrés, A. Shickova, R. O'cormor, G. Groeseneken, M. Heyns, S. De Gendt

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Resumen

Hf-based dielectrics layers with EOT<lnm are actively investigated for 22nm node and beyond. EOT scalability of these films can be achieved by simultaneously reducing the high-k thickness as well as optimizing the N-profile into the thin film. Electron traps are of concern for thick high-k while the scaling of EOT to 1 nm and below, the impact of these traps tends to disappear. PFET's with EOT ~1 nm shows a large hysteresis at high field in the Id-Vg characteristics, while no hysteresis is measured on the corresponding nmos devices. In this work we will prove by an advanced charge pumping technique that the hysteresis in pmos is caused by hole traps in the high-k. Furthermore, we show how NBTI defects are affected correlated with such hole traps. We will demonstrate how optimization of the nitridation process can strongly reduce the hole trap density. Phase separation in the HfSiON can be detected by this simple hole trap measurements.

Idioma originalInglés
Título de la publicación alojadaECS Transactions - Physics and Technology of High-k Gate Dielectrics 6
EditorialElectrochemical Society Inc.
Páginas77-84
Número de páginas8
Edición5
ISBN (versión impresa)9781566776516
DOI
EstadoPublicada - 2009
Publicado de forma externa
EventoPhysics and Technology of High-k Gate Dielectrics 6 - 214th ECS Meeting - Honolulu, HI, Estados Unidos
Duración: 13 oct. 200815 oct. 2008

Serie de la publicación

NombreECS Transactions
Número5
Volumen16
ISSN (versión impresa)1938-5862
ISSN (versión digital)1938-6737

Conferencia

ConferenciaPhysics and Technology of High-k Gate Dielectrics 6 - 214th ECS Meeting
País/TerritorioEstados Unidos
CiudadHonolulu, HI
Período13/10/0815/10/08

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