TY - GEN
T1 - Voltage and Technology Scaling of DMTJ-based STT-MRAMs for Energy-Efficient Embedded Memories
AU - Garzon, Esteban
AU - Taco, Ramiro
AU - Procel, Luis Miguel
AU - Trojman, Lionel
AU - Lanuzza, Marco
N1 - Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - This work presents energy advantages allowed by the technology and voltage scaling of spin-transfer torque mag-netic random access memories (STT-MRAMs) based on perpen-dicular double-barrier magnetic tunnel junction (DMTJ), with two reference layers. DMTJ is benchmarked against the single-barrier MTJ (SMTJ) -based alternative, and a comprehensive evaluation is carried out through a cross-layer simulation frame-work, considering state-of-the-art Verilog-A based SMTJ and DMTJ compact models, along with a 0.8V FinFET technology. Simulation results show that, thanks to the lower voltage op-erating point, DMTJ-based STT-MRAM allows energy savings for write/read operations of about 38%/45%, as compared to its SMTJ-based counterpart. Moreover, scaling from the 28 nm down to the 20 nm node, the DMTJ-based memory cell improves write/read energy of about 29%/33% at the expense of longer access times.
AB - This work presents energy advantages allowed by the technology and voltage scaling of spin-transfer torque mag-netic random access memories (STT-MRAMs) based on perpen-dicular double-barrier magnetic tunnel junction (DMTJ), with two reference layers. DMTJ is benchmarked against the single-barrier MTJ (SMTJ) -based alternative, and a comprehensive evaluation is carried out through a cross-layer simulation frame-work, considering state-of-the-art Verilog-A based SMTJ and DMTJ compact models, along with a 0.8V FinFET technology. Simulation results show that, thanks to the lower voltage op-erating point, DMTJ-based STT-MRAM allows energy savings for write/read operations of about 38%/45%, as compared to its SMTJ-based counterpart. Moreover, scaling from the 28 nm down to the 20 nm node, the DMTJ-based memory cell improves write/read energy of about 29%/33% at the expense of longer access times.
KW - Double-barrier magnetic tunnel junction (DMTJ)
KW - FinFET
KW - STT-MRAM
KW - embedded memory
KW - energy-efficient
KW - low-voltage
UR - http://www.scopus.com/inward/record.url?scp=85133202392&partnerID=8YFLogxK
U2 - 10.1109/LASCAS53948.2022.9789054
DO - 10.1109/LASCAS53948.2022.9789054
M3 - Contribución a la conferencia
AN - SCOPUS:85133202392
T3 - 2022 IEEE 13th Latin American Symposium on Circuits and Systems, LASCAS 2022
BT - 2022 IEEE 13th Latin American Symposium on Circuits and Systems, LASCAS 2022
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 13th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2022
Y2 - 1 March 2022 through 4 March 2022
ER -