XNOR-Bitcount Operation Exploiting Computing-In-Memory With STT-MRAMs

Ariana Musello; Esteban Garzon; Marco Lanuzza; Luis Miguel Procel; Ramiro Taco

doi:10.1109/TCSII.2023.3241163

XNOR-Bitcount Operation Exploiting Computing-In-Memory With STT-MRAMs

Ariana Musello, Esteban Garzon, Marco Lanuzza, Luis Miguel Procel, Ramiro Taco

Electronic Design Automation Group

Producción científica: Contribución a una revista › Artículo › revisión exhaustiva

15 Citas (Scopus)

Resumen

This brief presents an energy-efficient and high-performance XNOR-bitcount architecture exploiting the benefits of computing-in-memory (CiM) and unique properties of spin-transfer torque magnetic RAM (STT-MRAM) based on double-barrier magnetic tunnel junctions (DMTJs). Our work proposes hardware and algorithmic optimizations, benchmarked against a state-of-the-art CiM-based XNOR-bitcount design. Simulation results show that our hardware optimization reduces the storage requirement (-50%) for each XNOR-bitcount operation. The proposed algorithmic optimization improves execution time and energy consumption by about 30% (78%) and 26% (85%), respectively, for single (5 sequential) 9-bit XNOR-bitcount operations. As a case study, our solution is demonstrated for shape analysis using bit-quads.

Idioma original	Inglés
Páginas (desde-hasta)	1259-1263
Número de páginas	5
Publicación	IEEE Transactions on Circuits and Systems II: Express Briefs
Volumen	70
N.º	3
DOI	https://doi.org/10.1109/TCSII.2023.3241163
Estado	Publicada - 1 mar. 2023

ODS de las Naciones Unidas

Este resultado contribuye a los siguientes Objetivos de Desarrollo Sostenible

Acceder al documento

10.1109/TCSII.2023.3241163

Otros archivos y enlaces

Enlace a la publicación en Scopus

Citar esto

@article{9a0951559c4747a884fec36b2cfa54a0,

title = "XNOR-Bitcount Operation Exploiting Computing-In-Memory With STT-MRAMs",

abstract = "This brief presents an energy-efficient and high-performance XNOR-bitcount architecture exploiting the benefits of computing-in-memory (CiM) and unique properties of spin-transfer torque magnetic RAM (STT-MRAM) based on double-barrier magnetic tunnel junctions (DMTJs). Our work proposes hardware and algorithmic optimizations, benchmarked against a state-of-the-art CiM-based XNOR-bitcount design. Simulation results show that our hardware optimization reduces the storage requirement (-50%) for each XNOR-bitcount operation. The proposed algorithmic optimization improves execution time and energy consumption by about 30% (78%) and 26% (85%), respectively, for single (5 sequential) 9-bit XNOR-bitcount operations. As a case study, our solution is demonstrated for shape analysis using bit-quads.",

keywords = "BNN, CNN, Computing-in-memory, DMTJ, MAC, STT-MRAM, XNOR-bitcount, bit-quad, spin-transfer torque",

author = "Ariana Musello and Esteban Garzon and Marco Lanuzza and Procel, {Luis Miguel} and Ramiro Taco",

note = "Publisher Copyright: {\textcopyright} 2004-2012 IEEE.",

year = "2023",

month = mar,

day = "1",

doi = "10.1109/TCSII.2023.3241163",

language = "Ingl{\'e}s",

volume = "70",

pages = "1259--1263",

journal = "IEEE Transactions on Circuits and Systems II: Express Briefs",

issn = "1549-7747",

number = "3",

}

TY - JOUR

T1 - XNOR-Bitcount Operation Exploiting Computing-In-Memory With STT-MRAMs

AU - Musello, Ariana

AU - Garzon, Esteban

AU - Lanuzza, Marco

AU - Procel, Luis Miguel

AU - Taco, Ramiro

PY - 2023/3/1

Y1 - 2023/3/1

N2 - This brief presents an energy-efficient and high-performance XNOR-bitcount architecture exploiting the benefits of computing-in-memory (CiM) and unique properties of spin-transfer torque magnetic RAM (STT-MRAM) based on double-barrier magnetic tunnel junctions (DMTJs). Our work proposes hardware and algorithmic optimizations, benchmarked against a state-of-the-art CiM-based XNOR-bitcount design. Simulation results show that our hardware optimization reduces the storage requirement (-50%) for each XNOR-bitcount operation. The proposed algorithmic optimization improves execution time and energy consumption by about 30% (78%) and 26% (85%), respectively, for single (5 sequential) 9-bit XNOR-bitcount operations. As a case study, our solution is demonstrated for shape analysis using bit-quads.

AB - This brief presents an energy-efficient and high-performance XNOR-bitcount architecture exploiting the benefits of computing-in-memory (CiM) and unique properties of spin-transfer torque magnetic RAM (STT-MRAM) based on double-barrier magnetic tunnel junctions (DMTJs). Our work proposes hardware and algorithmic optimizations, benchmarked against a state-of-the-art CiM-based XNOR-bitcount design. Simulation results show that our hardware optimization reduces the storage requirement (-50%) for each XNOR-bitcount operation. The proposed algorithmic optimization improves execution time and energy consumption by about 30% (78%) and 26% (85%), respectively, for single (5 sequential) 9-bit XNOR-bitcount operations. As a case study, our solution is demonstrated for shape analysis using bit-quads.

KW - BNN

KW - CNN

KW - Computing-in-memory

KW - DMTJ

KW - MAC

KW - STT-MRAM

KW - XNOR-bitcount

KW - bit-quad

KW - spin-transfer torque

UR - http://www.scopus.com/inward/record.url?scp=85148478699&partnerID=8YFLogxK

U2 - 10.1109/TCSII.2023.3241163

DO - 10.1109/TCSII.2023.3241163

M3 - Artículo

AN - SCOPUS:85148478699

SN - 1549-7747

VL - 70

SP - 1259

EP - 1263

JO - IEEE Transactions on Circuits and Systems II: Express Briefs

JF - IEEE Transactions on Circuits and Systems II: Express Briefs

IS - 3

ER -

XNOR-Bitcount Operation Exploiting Computing-In-Memory With STT-MRAMs

Resumen

ODS de las Naciones Unidas

Acceder al documento

Otros archivos y enlaces

Huella

Citar esto